-- GSI 8161Z18 TQFP J T A G S O F T W A R E
-- BSDL File Generated: 6th April 2005
--
-- Revision History:
-- Rev B 10/23/06 1) Swapped pin mapping for E2 and E1
-- 2) Reordered Address pins
--
entity GS8161Z18BTQ is
generic (PHYSICAL_PIN_MAP : string := "TQ_PACKAGE");
port (
ADDR: in bit_vector(0 to 19);
CK: in bit;
Ba: in bit;
Bb: in bit;
W: in bit;
E1: in bit;
E2: in bit;
E3: in bit;
G: in bit;
CKE: in bit;
ADV: in bit;
DQa: inout bit_vector(1 to 9);
DQb: inout bit_vector(1 to 9);
DP: in bit;
QE: buffer bit;
ZZ: in bit;
FT: in bit;
LBO: in bit;
TMS: in bit;
TDI: in bit;
TDO: out bit;
TCK: in bit;
VDD: linkage bit_vector(0 to 3);
VSS: linkage bit_vector(0 to 11);
VDDQ: linkage bit_vector(0 to 7);
NC: linkage bit_vedtor(0 to 18)
);
use STD_1149_1_1990.all;
attribute PIN_MAP of GS8161Z18BTQ : entity is PHYSICAL_PIN_MAP;
constant TQ_PACKAGE : PIN_MAP_STRING :=
"CK: 89, " &
"ADDR:(37,36,35,34,33,32,100,99,84,83,82,81,80,50,49,48,47,46,45,44), " &
"Ba: 93, " &
"Bb: 94, " &
"W: 88, " &
"E1: 98, " &
"E2: 97, " &
"E3: 92, " &
"G: 86, " &
"CKE: 87, " &
"ADV: 85, " &
"DQa: (58,59,62,63,68,69,72,73,74), " &
"DQb: (8,9,12,13,18,19,22,23,24), " &
"DP: 16, " &
"ZZ: 64, " &
"QE: 66, " &
"FT: 14, " &
"LBO: 31, " &
"TMS: 38, " &
"TDI: 39, " &
"TDO: 42, " &
"TCK: 43, " &
"VDD: (15,41,65,91), " &
"VSS: (5,10,17,21,26,40,55,60,67,71,76,90), " &
"VDDQ: (4,11,20,27,54,61,70,77)," &
"NC: (1,2,3,6,7,25,28,29,30,51,52,53,56,57,75,78,79,95,96)";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute INSTRUCTION_LENGTH of GS8161Z18BTQ : entity is 3;
attribute INSTRUCTION_OPCODE of GS8161Z18BTQ : entity is
"EXTEST (000)," &
"SAMPLE (100)," &
"IDCODE (001)," &
"SAMPLZ (010)," &
"BYPASS (111)";
attribute INSTRUCTION_CAPTURE of GS8161Z18BTQ : entity is "001";
attribute IDCODE_REGISTER of GS8161Z18BTQ : entity is
"00000000000000010000000110110011";
attribute REGISTER_ACCESS of GS8161Z18BTQ : entity is
"BOUNDARY (EXTEST,SAMPLE,SAMPLZ),"&
"IDCODE (IDCODE),"&
"BYPASS (BYPASS)";
attribute BOUNDARY_CELLS of GS8161Z18BTQ : entity is
"BC_1,BC_4";
attribute BOUNDARY_LENGTH of GS8161Z18BTQ : entity is 117;
attribute BOUNDARY_REGISTER of GS8161Z18BTQ : entity is
-- num cell port func safe [ccell disval rslt]
"0 (BC_4, * ,internal, X)," &
"1 (BC_4, * ,internal, X)," &
"2 (BC_4, * ,internal, X)," &
"3 (BC_1, ADDR(19), input, X)," &
"4 (BC_1, ADDR(18), input, X)," &
"5 (BC_1, ADDR(17), input, X)," &
"6 (BC_1, ADDR(16), input, X)," &
"7 (BC_1, ADDR(15), input, X)," &
"8 (BC_1, ADDR(14), input, X)," &
"9 (BC_1, ADDR(13), input, X)," &
"10 (BC_4, * ,internal, X)," &
"11 (BC_4, * ,internal, X)," &
"12 (BC_4, * ,internal, X)," &
"13 (BC_4, * ,internal, X)," &
"14 (BC_4, * ,internal, X)," &
"15 (BC_4, * ,internal, X)," &
"16 (BC_4, * ,internal, X)," &
"17 (BC_4, * ,internal, X)," &
"18 (BC_4, * ,internal, X)," &
"19 (BC_4, * ,internal, X)," &
"20 (BC_1, DQa(1), output3, X, 116, 0, Z)," &
"21 (BC_1, DQa(1), input, X)," &
"22 (BC_1, DQa(2), output3, X, 116, 0, Z)," &
"23 (BC_1, DQa(2), input, X)," &
"24 (BC_1, DQa(3), output3, X, 116, 0, Z)," &
"25 (BC_1, DQa(3), input, X)," &
"26 (BC_1, DQa(4), output3, X, 116, 0, Z)," &
"27 (BC_1, DQa(4), input, X)," &
"28 (BC_1, ZZ , input, X)," &
"29 (BC_4, * ,internal, X)," &
"30 (BC_1, DQa(5), output3, X, 116, 0, Z)," &
"31 (BC_1, DQa(5), input, X)," &
"32 (BC_1, DQa(6), output3, X, 116, 0, Z)," &
"33 (BC_1, DQa(6), input, X)," &
"34 (BC_1, DQa(7), output3, X, 116, 0, Z)," &
"35 (BC_1, DQa(7), input, X)," &
"36 (BC_1, DQa(8), output3, X, 116, 0, Z)," &
"37 (BC_1, DQa(8), input, X)," &
"38 (BC_1, DQa(9), output3, X, 116, 0, Z)," &
"39 (BC_1, DQa(9), input, X)," &
"40 (BC_4, * ,internal, X)," &
"41 (BC_4, * ,internal, X)," &
"42 (BC_4, * ,internal, X)," &
"43 (BC_4, * ,internal, X)," &
"44 (BC_4, * ,internal, X)," &
"45 (BC_4, * ,internal, X)," &
"46 (BC_4, * ,internal, X)," &
"47 (BC_4, * ,internal, X)," &
"48 (BC_1, ADDR(12), input, X)," &
"49 (BC_1, ADDR(11), input, X)," &
"50 (BC_1, ADDR(10), input, X)," &
"51 (BC_1, ADDR(9) , input, X)," &
"52 (BC_1, ADDR(8) , input, X)," &
"53 (BC_1, ADV, input, X)," &
"54 (BC_1, G, input, X)," &
"55 (BC_1, CKE, input, X)," &
"56 (BC_1, W, input, X)," &
"57 (BC_1, CK, input, X)," &
"58 (BC_4, * ,internal, X)," &
"59 (BC_4, * ,internal, X)," &
"60 (BC_4, * ,internal, X)," &
"61 (BC_4, * ,internal, X)," &
"62 (BC_1, E3, input, X)," &
"63 (BC_1, Ba, input, X)," &
"64 (BC_4, * ,internal, X)," &
"65 (BC_1, Bb, input, X)," &
"66 (BC_4, * ,internal, X)," &
"67 (BC_1, E2, input, X)," &
"68 (BC_1, E1, input, X)," &
"69 (BC_1, ADDR(7), input, X)," &
"70 (BC_1, ADDR(6), input, X)," &
"71 (BC_4, * ,internal, X)," &
"72 (BC_4, * ,internal, X)," &
"73 (BC_4, * ,internal, X)," &
"74 (BC_4, * ,internal, X)," &
"75 (BC_4, * ,internal, X)," &
"76 (BC_4, * ,internal, X)," &
"77 (BC_4, * ,internal, X)," &
"78 (BC_4, * ,internal, X)," &
"79 (BC_4, * ,internal, X)," &
"80 (BC_4, * ,internal, X)," &
"81 (BC_1, DQb(1), output3, X, 116, 0, Z)," &
"82 (BC_1, DQb(1), input, X)," &
"83 (BC_1, DQb(2), output3, X, 116, 0, Z)," &
"84 (BC_1, DQb(2), input, X)," &
"85 (BC_1, DQb(3), output3, X, 116, 0, Z)," &
"86 (BC_1, DQb(3), input, X)," &
"87 (BC_1, DQb(4), output3, X, 116, 0, Z)," &
"88 (BC_1, DQb(4), input, X)," &
"89 (BC_1, FT, input, X)," &
"90 (BC_4, * ,internal, X)," &
"91 (BC_1, DQb(5), output3, X, 116, 0, Z)," &
"92 (BC_1, DQb(5), input, X)," &
"93 (BC_1, DQb(6), output3, X, 116, 0, Z)," &
"94 (BC_1, DQb(6), input, X)," &
"95 (BC_1, DQb(7), output3, X, 116, 0, Z)," &
"96 (BC_1, DQb(7), input, X)," &
"97 (BC_1, DQb(8), output3, X, 116, 0, Z)," &
"98 (BC_1, DQb(8), input, X)," &
"99 (BC_1, DQb(9), output3, X, 116, 0, Z)," &
"100 (BC_1, DQb(9), input, X)," &
"101 (BC_4, * ,internal, X)," &
"102 (BC_4, * ,internal, X)," &
"103 (BC_4, * ,internal, X)," &
"104 (BC_4, * ,internal, X)," &
"105 (BC_4, * ,internal, X)," &
"106 (BC_4, * ,internal, X)," &
"107 (BC_4, * ,internal, X)," &
"108 (BC_4, * ,internal, X)," &
"109 (BC_1, LBO, input, X)," &
"110 (BC_1, ADDR(5), input, X)," &
"111 (BC_1, ADDR(4), input, X)," &
"112 (BC_1, ADDR(3), input, X)," &
"113 (BC_1, ADDR(2), input, X)," &
"114 (BC_1, ADDR(1), input, X)," &
"115 (BC_1, ADDR(0), input, X)," &
"116 (BC_1, *, control, 0)" ;
end GS8161Z18BTQ;