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ChipVORX ISP IP for Ultra Fast Flash Programming
BSDL File: IDT72T18105 Download View details  


idt72t18105.bsdl0000775000263300015630000002535011167210724012761 0ustar  cmsfcmdesign-- Boundary Scan Description Language (BSDL) for IDT72T18105
-- BSDL revision : 1.0
-- Date created  : 03/11/2005
-- Last updated  : 03/11/2005
-- Packages      : 240-Pin BGA

entity idt72t18105 is
    generic (PHYSICAL_PIN_MAP : string :=  "BB240");
    port (
        D                       :in             bit_vector(0 to 17);
        IW                      :in             bit;
        SCLK                    :in             bit;
        SENB                    :in             bit;
        WENB                    :in             bit;
        WCSB                    :in             bit;
        WCLK                    :in             bit;
        PRSB                    :in             bit;
        MRSB                    :in             bit;
        MARK                    :in             bit;
        ASYRB                   :in             bit;
        ASYWB                   :in             bit;
        ERCLK                   :buffer         bit;
        ERENB                   :buffer         bit;
        SHSTL                   :in             bit;
        WHSTL                   :in             bit;
        LDB                     :in             bit;
        FWFTSI                  :in             bit;
        FF                      :buffer         bit;
        PAF                     :buffer         bit;
        OW                      :in             bit;
        FSEL                    :in             bit_vector(0 to 1);
        HF                      :buffer         bit;
        BEB                     :in             bit;
        IP                      :in             bit;
        PFM                     :in             bit;
        PAE                     :buffer         bit;
        EF                      :buffer         bit;
        RCLK                    :in             bit;
        RENB                    :in             bit;
        RHSTL                   :in             bit;
        RTB                     :in             bit;
        OEB                     :in             bit;
        RCSB                    :in             bit;
        Q                       :buffer         bit_vector(0 to 17);
        TCK                     :in             bit;
        TMS                     :in             bit;
        TDI                     :in             bit;
        TRSTB                   :in             bit;
        TDO                     :out            bit;
        VREF                    :linkage        bit;
        DNC                     :linkage        bit_vector(0 to 36);
        GND                     :linkage        bit_vector(0 to 50);
        VDDQ                    :linkage        bit_vector(0 to 37);
        VDD                     :linkage        bit_vector(0 to 37)
    );

    use STD_1149_1_1994.all;

    attribute COMPONENT_CONFORMANCE of idt72t18105 : entity is
    "STD_1149_1_1993";

    attribute PIN_MAP of idt72t18105 : entity is PHYSICAL_PIN_MAP;

    constant BB240 : PIN_MAP_STRING :=
        "WCLK   : A7,  "&
        "PRSB   : A8,  "&
        "FF     : A10, "&
        "ERENB  : A11, "&
        "RCLK   : A12, "&
        "OEB    : A13, "&
        "WENB   : B7,  "&
        "MRSB   : B8,  "&
        "PAF    : B10, "&
        "EF     : B11, "&
        "RENB   : B12, "&
        "RCSB   : B13, "&
        "WCSB   : C7,  "&
        "LDB    : C8,  "&
        "HF     : C10, "&
        "PAE    : C11, "&
        "MARK   : C12, "&
        "RTB    : C13, "&
        "FWFTSI : D4,  "&
        "OW     : D5,  "&
        "FSEL   : (D6, D8), "&
        "SHSTL  : D7,  "&
        "BEB    : D10, "&
        "IP     : D11, "&
        "RHSTL  : D13, "&
        "ASYRB  : D14, "&
        "PFM    : D15, "&
        "SENB   : G2,  "&
        "SCLK   : G3,  "&
        "WHSTL  : G4,  "&
        "ASYWB  : H4,  "&
        "VREF   : J4,  "&
        "IW     : K4,  "&
        "TMS    : T8,  "&
        "TDO    : T9,  "&
        "TRSTB  : U8,  "&
        "TDI    : U9,  "&
        "TCK    : V9,  "&
        "ERCLK  : V11, "&
        "D      : (V8,  T7,  U7,  V7,  T6,  T5,  V6,  U5,  U6,  "&
	         " V5,  T4,  U4,  V4,  T3,  U3,  V3,  V2,  U2), "&
        "Q      : (T11, U11, T12, T13, V12, U13, U12, V13, T14, "&
	         " U14, V14, T15, U15, V15, T16, U16, V16, V17),"&
        "DNC    : (U1,  T1,  T2,  R1,  R2,  R3,  P1,  P2,  P3,  N1,  "&
	         " N2,  N3,  M1,  M2,  M3,  L1,  L2,  L3,  U17, U18, "&
		 " T18, T17, R18, R17, R16, P18, P17, P16, N18, N17, "&
		 " N16, M18, M17, M16, L18, L17, D12), "&
        "VDDQ   : (A14, A15, A16, A17, A18, B14, B15, B16, B17, B18,"&
		 " C14, C15, C16, C17, C18, D16, D17, D18, E16, E17,"&
		 " E18, F16, F17, F18, G16, G17, G18, H16, H17, H18,"&
		 " J16, J17, J18, K16, K17, K18, L16, V18), "&
        "VDD    : (A1,  A2,  A3,  A4,  A5,  A6,  B1,  B2,  B3,  B4, "&
	         " B5,  B6,  C1,  C2,  C3,  C4,  C5,  C6,  D1,  D2, "&
		 " D3,  E1,  E2,  E3,  F1,  F2,  F3,  G1,  H1,  H2, "&
		 " H3,  J1,  J2,  J3,  K1,  K2,  K3,  V1),  "&
        "GND    : (A9,  B9,  C9,  D9,  E4,  E15, F4,  F15, G15, H8, "&
	         " H9,  H10, H11, H15, J8,  J9,  J10, J11, J15, K8, "&
		 " K9,  K10, K11, K15, L4,  L8,  L9,  L10, L11, L15,"&
		 " M4,  M15, N4,  N15, P4,  P15, R4,  R5,  R6,  R7, "&
		 " R8,  R9,  R10, R11, R12, R13, R14, R15, T10, U10,"&
		 " V10)";

    --Scan port identification
    attribute TAP_SCAN_IN    of tdi   : signal is true;
    attribute TAP_SCAN_MODE  of tms   : signal is true;
    attribute TAP_SCAN_OUT   of tdo   : signal is true;
    attribute TAP_SCAN_CLOCK of tck   : signal is (1.0e7, LOW);
    attribute TAP_SCAN_RESET of trstb : signal is true;

    --Compliance to avoid oe issue
    attribute COMPLIANCE_PATTERNS of idt72t18105: entity is
        "(PRSB, OEB, IW, OW, WHSTL, RHSTL, SHSTL) (0000111)";

    --TAP Description
    attribute INSTRUCTION_LENGTH of idt72t18105 : entity is 4;
    attribute INSTRUCTION_OPCODE of idt72t18105 : entity is
        "EXTEST          (0000)," &
        "SAMPLE          (0001)," &
        "IDCODE          (0010)," &
        "HIGHZ           (0011)," &
        "BYPASS          (1111)";
    attribute INSTRUCTION_CAPTURE of idt72t18105 : entity is "1101";

    attribute IDCODE_REGISTER of idt72t18105 : entity is
        "0000" &                -- version
        "0000010000011001" &    -- part number
        "00000110011" &         -- manufacturer's identity
        "1";                    -- required by 1149.1
    --  Part IDCODE:
    --  18105 "0000-0100-0001-1001" --0419
    --  18115 "0000-0100-0001-1000" --0418
    --  18125 "0000-0100-0001-0111" --0417

    attribute REGISTER_ACCESS of idt72t18105 : entity is
        "Bypass          (BYPASS, HIGHZ)," &
        "Boundary        (SAMPLE, EXTEST)," &
        "Device_ID       (IDCODE)";

    attribute BOUNDARY_LENGTH of idt72t18105 : entity is 70;

    attribute BOUNDARY_REGISTER  of idt72t18105 : entity is
     --
     -- num   cell   port     function safe[ccell disval rslt]
     --
        "69  (BC_0,  D(0),       input,      X)," &
        "68  (BC_0,  D(1),       input,      X)," &
        "67  (BC_0,  D(2),       input,      X)," &
        "66  (BC_0,  D(3),       input,      X)," &
        "65  (BC_0,  D(4),       input,      X)," &
        "64  (BC_0,  D(5),       input,      X)," &
        "63  (BC_0,  D(6),       input,      X)," &
        "62  (BC_0,  D(7),       input,      X)," &
        "61  (BC_0,  D(8),       input,      X)," &
        "60  (BC_0,  D(9),       input,      X)," &
        "59  (BC_0,  D(10),      input,      X)," &
        "58  (BC_0,  D(11),      input,      X)," &
        "57  (BC_0,  D(12),      input,      X)," &
        "56  (BC_0,  D(13),      input,      X)," &
        "55  (BC_0,  D(14),      input,      X)," &
        "54  (BC_0,  D(15),      input,      X)," &
        "53  (BC_0,  D(16),      input,      X)," &
        "52  (BC_0,  D(17),      input,      X)," &
        "51  (BC_0,  *,          internal,   X)," &
      --"51  (BC_0,  IW,         input,      X)," &
        "50  (BC_0,  SCLK,       input,      X)," &
        "49  (BC_0,  SENB,       input,      X)," &
        "48  (BC_0,  ASYWB,      input,      X)," &
        "47  (BC_0,  *,          internal,   X)," &
      --"47  (BC_0,  WHSTL,      input,      X)," &
        "46  (BC_0,  WENB,       input,      X)," &
        "45  (BC_0,  WCSB,       input,      X)," &
        "44  (BC_0,  WCLK,       input,      X)," &
        "43  (BC_0,  *,          internal,   X)," &
      --"43  (BC_0,  PRSB,       input,      X)," &
        "42  (BC_0,  MRSB,       input,      X)," &
        "41  (BC_0,  LDB,        input,      X)," &
        "40  (BC_0,  FWFTSI,     input,      X)," &
        "39  (BC_0,  FF,         output2,    X)," &
        "38  (BC_0,  PAF,        output2,    X)," &
        "37  (BC_0,  *,          internal,   X)," &
      --"37  (BC_0,  OW,         input,      X)," &
        "36  (BC_0,  FSEL(0),    input,      X)," &
        "35  (BC_0,  HF,         output2,    X)," &
        "34  (BC_0,  *,          internal,   X)," &
      --"34  (BC_0,  SHSTL,      input,      X)," &
        "33  (BC_0,  FSEL(1),    input,      X)," &
        "32  (BC_0,  BEB,        input,      X)," &
        "31  (BC_0,  IP,         input,      X)," &
        "30  (BC_0,  *,          internal,   X)," &
      --"30  (BC_0,  RHSTL,      input,      X)," &
        "29  (BC_0,  ASYRB,      input,      X)," &
        "28  (BC_0,  PAE,        output2,    X)," &
        "27  (BC_0,  PFM,        input,      X)," &
        "26  (BC_0,  EF,         output2,    X)," &
        "25  (BC_0,  ERENB,      output2,    X)," &
        "24  (BC_0,  MARK,       input,      X)," &
        "23  (BC_0,  RCLK,       input,      X)," &
        "22  (BC_0,  RENB,       input,      X)," &
        "21  (BC_0,  RTB,        input,      X)," &
        "20  (BC_0,  RCSB,       input,      X)," &
        "19  (BC_0,  *,          internal,   X)," &
      --"19  (BC_0,  OEB,        input,      X)," &
        "18  (BC_0,  Q(17),      output2,    X)," &
        "17  (BC_0,  Q(16),      output2,    X)," &
        "16  (BC_0,  Q(15),      output2,    X)," &
        "15  (BC_0,  Q(14),      output2,    X)," &
        "14  (BC_0,  Q(13),      output2,    X)," &
        "13  (BC_0,  Q(12),      output2,    X)," &
        "12  (BC_0,  Q(11),      output2,    X)," &
        "11  (BC_0,  Q(10),      output2,    X)," &
        "10  (BC_0,  Q(9),       output2,    X)," &
        "9   (BC_0,  Q(8),       output2,    X)," &
        "8   (BC_0,  Q(7),       output2,    X)," &
        "7   (BC_0,  Q(6),       output2,    X)," &
        "6   (BC_0,  Q(5),       output2,    X)," &
        "5   (BC_0,  Q(4),       output2,    X)," &
        "4   (BC_0,  Q(3),       output2,    X)," &
        "3   (BC_0,  Q(2),       output2,    X)," &
        "2   (BC_0,  Q(1),       output2,    X)," &
        "1   (BC_0,  Q(0),       output2,    X)," &
        "0   (BC_0,  ERCLK,      output2,    X)";

end idt72t18105;


This library contains 7712 BSDL files (for 6084 distinct entities) from 63 vendors
Last BSDL model (KS32C41100) was added on Mar 9, 2017 20:54
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