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BSDL File: IDT2288 Download View details  


-- ***********************************************************************

--   BSDL file for design IDT2288

--   Created by Synopsys Version 1999.10 (Sep 02, 1999)

--   Designer: 
--   Company:  

--   Date: Mon Sep  1 17:22:27 2003

-- ***********************************************************************


 entity IDT2288 is
   
-- This section identifies the default device package selected.
   
   generic (PHYSICAL_PIN_MAP: string:= "PBGA256");
   
-- This section declares all the ports in the design.
   
   port ( 
          CSB          : in       bit;
          DSB_RDB_SCLK : in       bit;
          MPM          : in       bit;
          OSCI         : in       bit;
          RESETB       : in       bit;
          RWB_WRB_SDI  : in       bit;
          SPIEN        : in       bit;
          TCK          : in       bit;
          TDI          : in       bit;
          TEST_1544    : in       bit;
          TEST_2048    : in       bit;
          THZ          : in       bit;
          TMS          : in       bit;
          TRSTB        : in       bit;
          A            : in       bit_vector (0 to 10);
          CLK_SEL      : in       bit_vector (0 to 2);
          TSD          : in       bit_vector (1 to 8);
          TSIG         : in       bit_vector (1 to 8);
          D            : inout    bit_vector (0 to 7);
          GPIO         : inout    bit_vector (0 to 1);
          RSCK         : inout    bit_vector (1 to 8);
          RSFS         : inout    bit_vector (1 to 8);
          TSCK         : inout    bit_vector (1 to 8);
          TSFS         : inout    bit_vector (1 to 8);
          INTB         : out      bit;
          TDO          : out      bit;
          RSD          : out      bit_vector (1 to 8);
          RSIG         : out      bit_vector (1 to 8);
          CLK_GEN_1544 : buffer   bit;
          CLK_GEN_2048 : buffer   bit;
          REFA_OUT     : buffer   bit;
          REFB_OUT     : buffer   bit;
          TEST0        : linkage  bit;
          TESTSE       : linkage  bit;
          RRING        : linkage  bit_vector (1 to 8);
          RTIP         : linkage  bit_vector (1 to 8);
          REFR         : linkage  bit;
          TEST1        : linkage  bit;
          TEST2        : linkage  bit;
          VDDAB        : linkage  bit;
          VDDAP        : linkage  bit;
          VDDAR1       : linkage  bit;
          VDDAR2       : linkage  bit;
          VDDAR3       : linkage  bit;
          VDDAR4       : linkage  bit;
          VDDAR5       : linkage  bit;
          VDDAR6       : linkage  bit;
          VDDAR7       : linkage  bit;
          VDDAR8       : linkage  bit;
          VDDAT1       : linkage  bit;
          VDDAT2       : linkage  bit;
          VDDAT3       : linkage  bit;
          VDDAT4       : linkage  bit;
          VDDAT5       : linkage  bit;
          VDDAT6       : linkage  bit;
          VDDAT7       : linkage  bit;
          VDDAT8       : linkage  bit;
          VDDAX1       : linkage  bit;
          VDDAX2       : linkage  bit;
          VDDAX3       : linkage  bit;
          VDDAX4       : linkage  bit;
          VDDAX5       : linkage  bit;
          VDDAX6       : linkage  bit;
          VDDAX7       : linkage  bit;
          VDDAX8       : linkage  bit;
          GNDA         : linkage  bit_vector (1 to 28);
          GNDD         : linkage  bit_vector (1 to 26);
          NC           : linkage  bit_vector (1 to 17);
          VDDDC        : linkage  bit_vector (1 to 21);
          VDDIO        : linkage  bit_vector (1 to 9)
   );
   
   use STD_1149_1_1994.all;
   
   attribute COMPONENT_CONFORMANCE of 
   IDT2288: entity is 
     "STD_1149_1_1993";
   
   attribute PIN_MAP of IDT2288
   : entity is PHYSICAL_PIN_MAP;
   
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
   
     constant PBGA256: PIN_MAP_STRING := 
        "CSB          : R11," &
        "DSB_RDB_SCLK : N10," &
        "MPM          : M11," &
        "OSCI         : B13," &
        "RESETB       : A14," &
        "RWB_WRB_SDI  : P11," &
        "SPIEN        : N11," &
        "TCK          : T15," &
        "TDI          : T13," &
        "TEST0        : P12," &
        "TESTSE       : N12," &
        "TEST_1544    : C15," &
        "TEST_2048    : D16," &
        "THZ          : B16," &
        "TMS          : T14," &
        "TRSTB        : R13," &
        "A            : (M7, N7, P7, R7, T7, M8, N8, P8, R8, T8, P9)," &
        "CLK_SEL      : (D15, C14, B15)," &
        "RRING        : (D11, D9, D5, C4, G14, H13, M13, N15)," &
        "RTIP         : (C11, D8, D6, B4, F14, J13, L13, N14)," &
        "TSD          : (G2, G4, F2, F4, E2, E4, D2, C2)," &
        "TSIG         : (G3, F1, F3, E1, E3, D1, C1, B1)," &
        "D            : (M10, T10, R10, P10, M9, N9, T9, R9)," &
        "GPIO         : (E13, D13)," &
        "RSCK         : (T6, P6, M6, R5, N5, T4, P4, T3)," &
        "RSFS         : (R6, N6, T5, P5, M5, R4, N4, R3)," &
        "TSCK         : (L3, L1, K3, K1, J3, J1, H2, H4)," &
        "TSFS         : (L2, K4, K2, J4, J2, H1, H3, G1)," &
        "INTB         : T11," &
        "TDO          : R14," &
        "RSD          : (P3, R2, R1, P1, N2, M4, M2, L5)," &
        "RSIG         : (T2, T1, P2, N3, N1, M3, M1, L4)," &
        "CLK_GEN_1544 : A16," &
        "CLK_GEN_2048 : D14," &
        "REFA_OUT     : A15," &
        "REFB_OUT     : B14," &
        "REFR         : C16," &
        "TEST1        : R12," &
        "TEST2        : T12," &
        "VDDAB        : D12," &
        "VDDAP        : A13," &
        "VDDAR1       : A10," &
        "VDDAR2       : C9," &
        "VDDAR3       : A5," &
        "VDDAR4       : A4," &
        "VDDAR5       : G16," &
        "VDDAR6       : H15," &
        "VDDAR7       : M15," &
        "VDDAR8       : N16," &
        "VDDAT1       : B12," &
        "VDDAT2       : B9," &
        "VDDAT3       : B5," &
        "VDDAT4       : A3," &
        "VDDAT5       : E15," &
        "VDDAT6       : H14," &
        "VDDAT7       : M16," &
        "VDDAT8       : P16," &
        "VDDAX1       : C12," &
        "VDDAX2       : B8," &
        "VDDAX3       : B7," &
        "VDDAX4       : B2," &
        "VDDAX5       : E14," &
        "VDDAX6       : J15," &
        "VDDAX7       : K15," &
        "VDDAX8       : R15," &
        "GNDA         : (B3, C3, D3, D4, C5, B6, C6, C7, D7, C8, B10, C10, " &
        "D10, B11, F13, G13, K13, N13, P13, J14, K14, L14, M14, P14, F15, " &
        "G15, L15, P15)," &
        "GNDD         : (E5, E6, F6, G6, E7, F7, G7, E8, F8, G8, E9, F9, G9" &
        ", H9, E10, F10, G10, H10, E11, F11, G11, H11, E12, F12, G12, H12)," &
        "NC           : (C13, A12, A8, A7, A1, E16, J16, K16, T16, A11, A9, " &
        "A6, A2, F16, H16, L16, R16)," &
        "VDDDC        : (H6, J6, K6, L6, H7, J7, K7, L7, H8, J8, K8, L8, J9" &
        ", K9, L9, J10, K10, L10, J11, K11, L11)," &
        "VDDIO        : (F5, G5, H5, J5, K5, J12, K12, L12, M12)";
   
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.
   
   attribute TAP_SCAN_CLOCK of TCK  : signal is (10.0e6, BOTH);
   attribute TAP_SCAN_IN    of TDI  : signal is true;
   attribute TAP_SCAN_MODE  of TMS  : signal is true;
   attribute TAP_SCAN_OUT   of TDO  : signal is true;
   attribute TAP_SCAN_RESET of TRSTB: signal is true;
   
-- Specifies the number of bits in the instruction register.
   
   attribute INSTRUCTION_LENGTH of 
   IDT2288: entity is 3;
   
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
   
   attribute INSTRUCTION_OPCODE of 
   IDT2288: entity is 
     "BYPASS (111)," &
     "EXTEST (000)," &
     "SAMPLE (010)," &
     "CLAMP  (011)," &
     "HIGHZ  (100)," &
     "USER1  (110)," &
     "IDCODE (001)," &
     "USER2  (101)";
   
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
   
   attribute INSTRUCTION_CAPTURE of 
   IDT2288: entity is "001";
   
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
   
   attribute IDCODE_REGISTER of 
   IDT2288: entity is 
     "0000" &                  -- 4-bit version number
     "0000010011010111" &      -- 16-bit part number
     "00000110011" &           -- 11-bit identity of the manufacturer
     "1";                      -- Required by IEEE Std 1149.1
   
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
   
   attribute REGISTER_ACCESS of 
   IDT2288: entity is 
        "BYPASS    (BYPASS, CLAMP, HIGHZ, USER1)," &
        "BOUNDARY  (EXTEST, SAMPLE)," &
        "DEVICE_ID (IDCODE)," &
        "UTDR1[20] (USER2)";
   
-- Specifies the length of the boundary scan register.
   
   attribute BOUNDARY_LENGTH of 
   IDT2288: entity is 173;
   
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
--      num     : Is the cell number.
--      cell    : Is the cell type as defined by the standard.
--      port    : Is the design port name. Control cells do not
--                have a port name.
--      function: Is the function of the cell as defined by the
--                standard. Is one of input, output2, output3,
--                bidir, control or controlr.
--      safe    : Specifies the value that the BSR cell should be
--                loaded with for safe operation when the software
--                might otherwise choose a random value.
--      ccell   : The control cell number. Specifies the control
--                cell that drives the output enable for this port.
--      disval  : Specifies the value that is loaded into the
--                control cell to disable the output enable for
--                the corresponding port.
--      rslt    : Resulting state. Shows the state of the driver
--                when it is disabled.
   
   attribute BOUNDARY_REGISTER of 
   IDT2288: entity is 
--    
--    num   cell   port          function      safe  [ccell  disval  rslt]
--    
     "172  (BC_4,  A(10),        observe_only, X),                        " &
     "171  (BC_4,  A(9),         observe_only, X),                        " &
     "170  (BC_4,  A(8),         observe_only, X),                        " &
     "169  (BC_4,  A(7),         observe_only, X),                        " &
     "168  (BC_4,  A(6),         observe_only, X),                        " &
     "167  (BC_4,  A(5),         observe_only, X),                        " &
     "166  (BC_4,  A(4),         observe_only, X),                        " &
     "165  (BC_4,  A(3),         observe_only, X),                        " &
     "164  (BC_4,  A(2),         observe_only, X),                        " &
     "163  (BC_4,  A(1),         observe_only, X),                        " &
     "162  (BC_4,  A(0),         observe_only, X),                        " &
     "161  (BC_1,  *,            control,      1),                        " &
     "160  (BC_4,  D(7),         observe_only, X),                        " &
     "159  (BC_1,  D(7),         output3,      X,    161,    1,      Z),  " &
     "158  (BC_4,  D(6),         observe_only, X),                        " &
     "157  (BC_1,  D(6),         output3,      X,    161,    1,      Z),  " &
     "156  (BC_4,  D(5),         observe_only, X),                        " &
     "155  (BC_1,  D(5),         output3,      X,    161,    1,      Z),  " &
     "154  (BC_4,  D(4),         observe_only, X),                        " &
     "153  (BC_1,  D(4),         output3,      X,    161,    1,      Z),  " &
     "152  (BC_4,  D(3),         observe_only, X),                        " &
     "151  (BC_1,  D(3),         output3,      X,    161,    1,      Z),  " &
     "150  (BC_4,  D(2),         observe_only, X),                        " &
     "149  (BC_1,  D(2),         output3,      X,    161,    1,      Z),  " &
     "148  (BC_4,  D(1),         observe_only, X),                        " &
     "147  (BC_1,  D(1),         output3,      X,    161,    1,      Z),  " &
     "146  (BC_4,  D(0),         observe_only, X),                        " &
     "145  (BC_1,  D(0),         output3,      X,    161,    1,      Z),  " &
     "144  (BC_4,  CSB,          observe_only, X),                        " &
     "143  (BC_4,  RWB_WRB_SDI,  observe_only, X),                        " &
     "142  (BC_4,  DSB_RDB_SCLK, observe_only, X),                        " &
     "141  (BC_4,  MPM,          observe_only, X),                        " &
     "140  (BC_4,  SPIEN,        observe_only, X),                        " &
     "139  (BC_1,  *,            control,      1),                        " &
     "138  (BC_1,  INTB,         output3,      X,    139,    1,      Z),  " &
     "137  (BC_1,  *,            controlr,     1),                        " &
     "136  (BC_4,  RSCK(1),      observe_only, X),                        " &
     "135  (BC_1,  RSCK(1),      output3,      X,    137,    1,      Z),"
      &
     "134  (BC_4,  RSFS(1),      observe_only, X),                        " &
     "133  (BC_1,  RSFS(1),      output3,      X,    137,    1,      Z),"
      &
     "132  (BC_1,  *,            controlr,     1),                        " &
     "131  (BC_4,  RSCK(2),      observe_only, X),                        " &
     "130  (BC_1,  RSCK(2),      output3,      X,    132,    1,      Z),"
      &
     "129  (BC_4,  RSFS(2),      observe_only, X),                        " &
     "128  (BC_1,  RSFS(2),      output3,      X,    132,    1,      Z),"
      &
     "127  (BC_1,  *,            controlr,     1),                        " &
     "126  (BC_4,  RSCK(3),      observe_only, X),                        " &
     "125  (BC_1,  RSCK(3),      output3,      X,    127,    1,      Z),"
      &
     "124  (BC_4,  RSFS(3),      observe_only, X),                        " &
     "123  (BC_1,  RSFS(3),      output3,      X,    127,    1,      Z),"
      &
     "122  (BC_1,  *,            controlr,     1),                        " &
     "121  (BC_4,  RSCK(4),      observe_only, X),                        " &
     "120  (BC_1,  RSCK(4),      output3,      X,    122,    1,      Z),"
      &
     "119  (BC_4,  RSFS(4),      observe_only, X),                        " &
     "118  (BC_1,  RSFS(4),      output3,      X,    122,    1,      Z),"
      &
     "117  (BC_1,  *,            controlr,     1),                        " &
     "116  (BC_4,  RSCK(5),      observe_only, X),                        " &
     "115  (BC_1,  RSCK(5),      output3,      X,    117,    1,      Z),"
      &
     "114  (BC_4,  RSFS(5),      observe_only, X),                        " &
     "113  (BC_1,  RSFS(5),      output3,      X,    117,    1,      Z),"
      &
     "112  (BC_1,  *,            controlr,     1),                        " &
     "111  (BC_4,  RSCK(6),      observe_only, X),                        " &
     "110  (BC_1,  RSCK(6),      output3,      X,    112,    1,      Z),"
      &
     "109  (BC_4,  RSFS(6),      observe_only, X),                        " &
     "108  (BC_1,  RSFS(6),      output3,      X,    112,    1,      Z),"
      &
     "107  (BC_1,  *,            controlr,     1),                        " &
     "106  (BC_4,  RSCK(7),      observe_only, X),                        " &
     "105  (BC_1,  RSCK(7),      output3,      X,    107,    1,      Z),"
      &
     "104  (BC_4,  RSFS(7),      observe_only, X),                        " &
     "103  (BC_1,  RSFS(7),      output3,      X,    107,    1,      Z),"
      &
     "102  (BC_1,  *,            controlr,     1),                        " &
     "101  (BC_4,  RSCK(8),      observe_only, X),                        " &
     "100  (BC_1,  RSCK(8),      output3,      X,    102,    1,      Z),"
      &
     "99   (BC_4,  RSFS(8),      observe_only, X),                        " &
     "98   (BC_1,  RSFS(8),      output3,      X,    102,    1,      Z),"
      &
     "97   (BC_1,  *,            controlr,     1),                        " &
     "96   (BC_1,  RSD(1),       output3,      X,    97,     1,      Z),  " &
     "95   (BC_1,  RSIG(1),      output3,      X,    97,     1,      Z),  " &
     "94   (BC_1,  *,            controlr,     1),                        " &
     "93   (BC_1,  RSD(2),       output3,      X,    94,     1,      Z),  " &
     "92   (BC_1,  RSIG(2),      output3,      X,    94,     1,      Z),  " &
     "91   (BC_1,  *,            controlr,     1),                        " &
     "90   (BC_1,  RSD(3),       output3,      X,    91,     1,      Z),  " &
     "89   (BC_1,  RSIG(3),      output3,      X,    91,     1,      Z),  " &
     "88   (BC_1,  *,            controlr,     1),                        " &
     "87   (BC_1,  RSD(4),       output3,      X,    88,     1,      Z),  " &
     "86   (BC_1,  RSIG(4),      output3,      X,    88,     1,      Z),  " &
     "85   (BC_1,  *,            controlr,     1),                        " &
     "84   (BC_1,  RSD(5),       output3,      X,    85,     1,      Z),  " &
     "83   (BC_1,  RSIG(5),      output3,      X,    85,     1,      Z),  " &
     "82   (BC_1,  *,            controlr,     1),                        " &
     "81   (BC_1,  RSD(6),       output3,      X,    82,     1,      Z),  " &
     "80   (BC_1,  RSIG(6),      output3,      X,    82,     1,      Z),  " &
     "79   (BC_1,  *,            controlr,     1),                        " &
     "78   (BC_1,  RSD(7),       output3,      X,    79,     1,      Z),  " &
     "77   (BC_1,  RSIG(7),      output3,      X,    79,     1,      Z),  " &
     "76   (BC_1,  *,            controlr,     1),                        " &
     "75   (BC_1,  RSD(8),       output3,      X,    76,     1,      Z),  " &
     "74   (BC_1,  RSIG(8),      output3,      X,    76,     1,      Z),  " &
     "73   (BC_1,  *,            controlr,     1),                        " &
     "72   (BC_4,  TSCK(1),      observe_only, X),                        " &
     "71   (BC_1,  TSCK(1),      output3,      X,    73,     1,      Z),"
      &
     "70   (BC_4,  TSFS(1),      observe_only, X),                        " &
     "69   (BC_1,  TSFS(1),      output3,      X,    73,     1,      Z),"
      &
     "68   (BC_1,  *,            controlr,     1),                        " &
     "67   (BC_4,  TSCK(2),      observe_only, X),                        " &
     "66   (BC_1,  TSCK(2),      output3,      X,    68,     1,      Z),"
      &
     "65   (BC_4,  TSFS(2),      observe_only, X),                        " &
     "64   (BC_1,  TSFS(2),      output3,      X,    68,     1,      Z),"
      &
     "63   (BC_1,  *,            controlr,     1),                        " &
     "62   (BC_4,  TSCK(3),      observe_only, X),                        " &
     "61   (BC_1,  TSCK(3),      output3,      X,    63,     1,      Z),"
      &
     "60   (BC_4,  TSFS(3),      observe_only, X),                        " &
     "59   (BC_1,  TSFS(3),      output3,      X,    63,     1,      Z),"
      &
     "58   (BC_1,  *,            controlr,     1),                        " &
     "57   (BC_4,  TSCK(4),      observe_only, X),                        " &
     "56   (BC_1,  TSCK(4),      output3,      X,    58,     1,      Z),"
      &
     "55   (BC_4,  TSFS(4),      observe_only, X),                        " &
     "54   (BC_1,  TSFS(4),      output3,      X,    58,     1,      Z),"
      &
     "53   (BC_1,  *,            controlr,     1),                        " &
     "52   (BC_4,  TSCK(5),      observe_only, X),                        " &
     "51   (BC_1,  TSCK(5),      output3,      X,    53,     1,      Z),"
      &
     "50   (BC_4,  TSFS(5),      observe_only, X),                        " &
     "49   (BC_1,  TSFS(5),      output3,      X,    53,     1,      Z),"
      &
     "48   (BC_1,  *,            controlr,     1),                        " &
     "47   (BC_4,  TSCK(6),      observe_only, X),                        " &
     "46   (BC_1,  TSCK(6),      output3,      X,    48,     1,      Z),"
      &
     "45   (BC_4,  TSFS(6),      observe_only, X),                        " &
     "44   (BC_1,  TSFS(6),      output3,      X,    48,     1,      Z),"
      &
     "43   (BC_1,  *,            controlr,     1),                        " &
     "42   (BC_4,  TSCK(7),      observe_only, X),                        " &
     "41   (BC_1,  TSCK(7),      output3,      X,    43,     1,      Z),"
      &
     "40   (BC_4,  TSFS(7),      observe_only, X),                        " &
     "39   (BC_1,  TSFS(7),      output3,      X,    43,     1,      Z),"
      &
     "38   (BC_1,  *,            controlr,     1),                        " &
     "37   (BC_4,  TSCK(8),      observe_only, X),                        " &
     "36   (BC_1,  TSCK(8),      output3,      X,    38,     1,      Z),"
      &
     "35   (BC_4,  TSFS(8),      observe_only, X),                        " &
     "34   (BC_1,  TSFS(8),      output3,      X,    38,     1,      Z),"
      &
     "33   (BC_4,  TSD(1),       observe_only, X),                        " &
     "32   (BC_4,  TSIG(1),      observe_only, X),                        " &
     "31   (BC_4,  TSD(2),       observe_only, X),                        " &
     "30   (BC_4,  TSIG(2),      observe_only, X),                        " &
     "29   (BC_4,  TSD(3),       observe_only, X),                        " &
     "28   (BC_4,  TSIG(3),      observe_only, X),                        " &
     "27   (BC_4,  TSD(4),       observe_only, X),                        " &
     "26   (BC_4,  TSIG(4),      observe_only, X),                        " &
     "25   (BC_4,  TSD(5),       observe_only, X),                        " &
     "24   (BC_4,  TSIG(5),      observe_only, X),                        " &
     "23   (BC_4,  TSD(6),       observe_only, X),                        " &
     "22   (BC_4,  TSIG(6),      observe_only, X),                        " &
     "21   (BC_4,  TSD(7),       observe_only, X),                        " &
     "20   (BC_4,  TSIG(7),      observe_only, X),                        " &
     "19   (BC_4,  TSD(8),       observe_only, X),                        " &
     "18   (BC_4,  TSIG(8),      observe_only, X),                        " &
     "17   (BC_4,  OSCI,         observe_only, X),                        " &
     "16   (BC_4,  RESETB,       observe_only, X),                        " &
     "15   (BC_1,  *,            control,      1),                        " &
     "14   (BC_4,  GPIO(1),      observe_only, X),                        " &
     "13   (BC_1,  GPIO(1),      output3,      X,    15,     1,      Z),"
      &
     "12   (BC_1,  *,            controlr,     1),                        " &
     "11   (BC_4,  GPIO(0),      observe_only, X),                        " &
     "10   (BC_1,  GPIO(0),      output3,      X,    12,     1,      Z),"
      &
     "9    (BC_4,  CLK_SEL(2),   observe_only, X),                        " &
     "8    (BC_4,  CLK_SEL(1),   observe_only, X),                        " &
     "7    (BC_4,  CLK_SEL(0),   observe_only, X),                        " &
     "6    (BC_4,  TEST_1544,    observe_only, X),                        " &
     "5    (BC_4,  TEST_2048,    observe_only, X),                        " &
     "4    (BC_1,  REFA_OUT,     output2,      X),                        " &
     "3    (BC_1,  REFB_OUT,     output2,      X),                        " &
     "2    (BC_1,  CLK_GEN_1544, output2,      X),                        " &
     "1    (BC_1,  CLK_GEN_2048, output2,      X),                        " &
     "0    (BC_4,  THZ,          observe_only, X)                         ";
 
 end IDT2288;

This library contains 7818 BSDL files (for 6184 distinct entities) from 66 vendors
Last BSDL model (LCMXO3L_6900C_XXBG256) was added on Nov 21, 2017 16:30
info@bsdl.info