BSDL Files Library for JTAG
The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BS/JTAG tools

ChipVORX ISP IP for Ultra Fast Flash Programming
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--------------------------------------------------------------------------------
--
--  VHDL Package and Package Body for isl5217 cells
--  Preliminary version -- 6/04/01
--  Revision 1.0 - 06/14/01
--
--  BIDIR_IN, EXTEST,  PI  pins P(15:0), IIN(19:0) and QIN(19:0) are not
--  supported in EXTEST mode, but are supported in SAMPLE mode.
--
--------------------------------------------------------------------------------
package isl5217_package is
  use STD_1149_1_1990.all;
  constant GEN_1: CELL_INFO;
end isl5217_package;

package body isl5217_package is
constant GEN_1: CELL_INFO :=
  ((BIDIR_IN, INTEST, PI),  (BIDIR_OUT, INTEST,  PI),
  (BIDIR_IN, EXTEST,  PI), (BIDIR_OUT, EXTEST,  CAP),
  (BIDIR_IN, SAMPLE,  PI),  (BIDIR_OUT, SAMPLE,  PI),
  (OUTPUT3, INTEST, PI),    (CONTROL, INTEST,  PI),
  (OUTPUT3, EXTEST, CAP),   (CONTROL, EXTEST,  CAP),
  (OUTPUT3, SAMPLE, PI),    (CONTROL, SAMPLE,  PI),
  (OUTPUT2, INTEST, PI),    (INPUT,   INTEST,  CAP),
  (OUTPUT2, EXTEST, CAP),   (INPUT,   EXTEST,  PI),
  (OUTPUT2, SAMPLE, PI),    (INPUT,   SAMPLE,  PI) );
end isl5217_package;  -- end of package body
--------------------------------------------------------------------------------


--------------------------------------------------------------------------------
--
--      Intersil ISL5217 BSDL
--      Quad Programmable Digital Up Converter
--      196 pin BGA
--      Preliminary version -- 06/04/01
--      Revision 1.0        -- 06/14/01 numerous revisions and changes
--      
--      
--      
--      
--      
--      
--------------------------------------------------------------------------------
entity ISL5217 is 
     
  generic (PHYSICAL_PIN_MAP : string := "BGA");
     
  port (SCLKA, SCLKB, SCLKC, SCLKD: buffer bit;
    FSRA, FSRB, FSRC, FSRD, SYNCO, ISTRB: buffer bit;
    OFFBIN, TRITST, OUTEN0, OUTEN1, CS: in bit;
    SDA, SDB, SDC, SDD: in bit;
    UPDA, UPDB, UPDC, UPDD: in bit;
    TXENA, TXENB, TXENC, TXEND: in bit;
    IOUT: out bit_vector(0 to 19);
    QOUT: out bit_vector(0 to 19);
    IIN: inout bit_vector(0 to 19);
    QIN: inout bit_vector(0 to 19);
    A: in bit_vector(0 to 6);
    P: inout bit_vector(0 to 15);    
    WR, RD, RDMODE, CLK, RESET: in bit;
    TDO: out bit;
    TDI, TMS, TCLK, TRST: in bit; 
    GND: linkage bit_vector(0 to 19); 
    VCCC: linkage bit_vector(0 to 11);
    VCCIO: linkage bit_vector(0 to 7);
    THERMAL: linkage bit_vector(0 to 15) );
  
  use STD_1149_1_1990.all;   -- Get Std 1149.1-1990 attributes and definitions
  use isl5217_package.all;  -- get isl5217 specific cells
     
  attribute PIN_MAP of ISL5217: entity is PHYSICAL_PIN_MAP;
     
  constant BGA: PIN_MAP_STRING := "CLK: G1, RESET: E4, RDMODE: L10, " &
    "ISTRB: F1, OFFBIN: K5, TRITST: F4, OUTEN0: G5, OUTEN1: F5, CS: H11, " &
    "A: (H10, G10, G14, G12, G13, F14, F10), WR: H13, RD: H14, P: (F11, F13, " &
    "E11, E13, D14, E12, C14, D12, C13, B14, B13, A14, A13, B12, C12, A12), " &
    "IIN: (P9, N8, P8, N7, P7, M6, P6, N5, P4, N3, P3, M3, P2, P1, N1, N2, " &
    "M1, M2, L1, J1), QIN: (N10, M9, L9, K9, M8, K8, L7, K7, L6, K6, M5, L5, " &
    "K4, L3, K3, K2, J3, H2, H3, G2), TXENA: N12, TXENB: P13, TXENC: N13, " &
    "TXEND: M13, UPDA: K11, UPDB: M12, UPDC: K13, UPDD: K12, SDA: P11, " &
    "SDB: M10, SDC: P12, SDD: M11, SCLKA: P14, SCLKB: N14, SCLKC: M14, " &
    "SCLKD: L14, FSRA: K10, FSRB: J12, FSRC: J11, FSRD: J14, SYNCO: J10, " &
    "IOUT: (A11, B10, A9, B8, A8, B7, A7, C7, A6, B5, A4, B3, A3, A2, A1, " &
    "B2, B1, C2, C1, D1), QOUT: (C10, D10, E10, C9, D9, E9, D8, E8, E7, " &
    "C6, D6, E6, C5, D5, E5, C4, C3, E2, E3, F3), VCCC: (D7, D11, D13, " &
    "E1, F2, G4, G11, J13, K14, L8, N6, P5), VCCIO: (A10, B4, B9, D4, L2, " &
    "L4, L11, N11), GND: (A5, B6, B11, C8, C11, D2, D3, E14, F12, G3, H12, " &
    "J2, K1, L12, L13, M4, M7, N4, N9, P10), TDO: J5, TDI: J4, TMS: H4, " &
    "TCLK: H1, TRST: H5, THERMAL: (F6, F7, F8, F9, G6, G7, G8, G9, H6, " &
    "H7, H8, H9, J6, J7, J8, J9) " ;

  attribute TAP_SCAN_CLOCK of TCLK: signal is (25.0e6, BOTH);  
  attribute TAP_SCAN_IN    of TDI : signal is true; 
  attribute TAP_SCAN_MODE  of TMS : signal is true; 
  attribute TAP_SCAN_OUT   of TDO : signal is true; 
  attribute TAP_SCAN_RESET of TRST: signal is true; 

  attribute INSTRUCTION_LENGTH of ISL5217: entity is 4; 
  attribute INSTRUCTION_OPCODE of ISL5217: entity is 
    "EXTEST (0000)," &          -- LSB is shifted in first
    "IDCODE (0001)," &
    "SAMPLE (0010)," &
    "INTEST (0011)," &
    "BYPASS (1111) " ;
  attribute INSTRUCTION_CAPTURE of ISL5217: entity is "0001"; 
  attribute INSTRUCTION_DISABLE of ISL5217: entity is "BYPASS";

  attribute IDCODE_REGISTER of ISL5217: entity is
    "0000"              &  -- 4 bit version number (rev0)
    "1100010000101001"  &  -- 16 bit part number (C429H = 50217) 
    "00000001011"       &  -- 11 bit manufacturing code 
    "1";                   -- 1 bit mandatory LSB

  attribute REGISTER_ACCESS of ISL5217: entity is 
    "BOUNDARY (EXTEST, SAMPLE, INTEST), "  &
    "BYPASS (BYPASS), " &  
    "IDCODE (IDCODE)";

  attribute BOUNDARY_CELLS of ISL5217: entity is "GEN_1"; 
  attribute BOUNDARY_LENGTH of ISL5217: entity is 231; 
  attribute BOUNDARY_REGISTER of ISL5217: entity is 
     
  -- num (cell, port/*,  function, safe, [ccell, disval, rslt])
     

    "0  (GEN_1, QOUT(19),     output3, 0,   1,  1,  Z),"  &   -- closest to TDO 
    "1  (GEN_1, *,            control,     1),"  &
    "2  (GEN_1, QOUT(18),     output3, 0,   3,  1,  Z),"  &
    "3  (GEN_1, *,            control,     1),"  &
    "4  (GEN_1, QOUT(17),     output3, 0,   5,  1,  Z),"  &
    "5  (GEN_1, *,            control,     1),"  &
    "6  (GEN_1, QOUT(16),     output3, 0,   7,  1,  Z),"  &
    "7  (GEN_1, *,            control,     1),"  &
    "8  (GEN_1, QOUT(15),     output3, 0,   9,  1,  Z),"  & 
    "9  (GEN_1, *,            control,     1),"  &
    "10  (GEN_1, QOUT(14) ,   output3, 0,   11,  1,  Z),"  & 
    "11  (GEN_1, *,           control,     1),"  &
    "12  (GEN_1, QOUT(13),    output3, 0,   13,  1,  Z),"  & 
    "13  (GEN_1, *,           control,     1),"  &
    "14  (GEN_1, QOUT(12),    output3, 0,   15,  1,  Z),"  & 
    "15  (GEN_1, *,           control,     1),"  &
    "16  (GEN_1, QOUT(11),    output3, 0,   17,  1,  Z),"  & 
    "17  (GEN_1, *,           control,     1),"  &
    "18  (GEN_1, QOUT(10),    output3, 0,   19,  1,  Z),"  & 
    "19  (GEN_1, *,           control,     1),"  &
    "20  (GEN_1, QOUT(9),     output3, 0,   21,  1,  Z),"  &
    "21  (GEN_1, *,           control,     1),"  &
    "22  (GEN_1, QOUT(8),     output3, 0,   23,  1,  Z),"  & 
    "23  (GEN_1, *,           control,     1),"  &
    "24  (GEN_1, QOUT(7),     output3, 0,   25,  1,  Z),"  & 
    "25  (GEN_1, *,           control,     1),"  &
    "26  (GEN_1, QOUT(6),     output3, 0,   27,  1,  Z),"  & 
    "27  (GEN_1, *,           control,     1),"  &
    "28  (GEN_1, QOUT(5),     output3, 0,   29,  1,  Z),"  & 
    "29  (GEN_1, *,           control,     1),"  &
    "30  (GEN_1, QOUT(4) ,    output3, 0,   31,  1,  Z),"  & 
    "31  (GEN_1, *,           control,     1),"  &
    "32  (GEN_1, QOUT(3),     output3, 0,   33,  1,  Z),"  & 
    "33  (GEN_1, *,           control,     1),"  &
    "34  (GEN_1, QOUT(2),     output3, 0,   35,  1,  Z),"  & 
    "35  (GEN_1, *,           control,     1),"  &
    "36  (GEN_1, QOUT(1),     output3, 0,   37,  1,  Z),"  & 
    "37  (GEN_1, *,           control,     1),"  &
    "38  (GEN_1, QOUT(0),     output3, 0,   39,  1,  Z),"  & 
    "39  (GEN_1, *,           control,     1),"  &
    "40  (GEN_1, IOUT(19),    output3, 0,   41,  1,  Z),"  &
    "41  (GEN_1, *,           control,     1),"  &
    "42  (GEN_1, IOUT(18),    output3, 0,   43,  1,  Z),"  &
    "43  (GEN_1, *,           control,     1),"  &
    "44  (GEN_1, IOUT(17),    output3, 0,   45,  1,  Z),"  & 
    "45  (GEN_1, *,           control,     1),"  &
    "46  (GEN_1, IOUT(16),    output3, 0,   47,  1,  Z),"  &
    "47  (GEN_1, *,           control,     1),"  &
    "48  (GEN_1, IOUT(15),    output3, 0,   49,  1,  Z),"  & 
    "49  (GEN_1, *,           control,     1),"  &
    "50  (GEN_1, IOUT(14) ,   output3, 0,   51,  1,  Z),"  & 
    "51  (GEN_1, *,           control,     1),"  &
    "52  (GEN_1, IOUT(13),    output3, 0,   53,  1,  Z),"  & 
    "53  (GEN_1, *,           control,     1),"  &
    "54  (GEN_1, IOUT(12),    output3, 0,   55,  1,  Z),"  & 
    "55  (GEN_1, *,           control,     1),"  &
    "56  (GEN_1, IOUT(11),    output3, 0,   57,  1,  Z),"  & 
    "57  (GEN_1, *,           control,     1),"  &
    "58  (GEN_1, IOUT(10),    output3, 0,   59,  1,  Z),"  & 
    "59  (GEN_1, *,           control,     1),"  &
    "60  (GEN_1, IOUT(9),     output3, 0,   61,  1,  Z),"  &
    "61  (GEN_1, *,           control,     1),"  &
    "62  (GEN_1, IOUT(8),     output3, 0,   63,  1,  Z),"  & 
    "63  (GEN_1, *,           control,     1),"  &
    "64  (GEN_1, IOUT(7),     output3, 0,   65,  1,  Z),"  & 
    "65  (GEN_1, *,           control,     1),"  &
    "66  (GEN_1, IOUT(6),     output3, 0,   67,  1,  Z),"  & 
    "67  (GEN_1, *,           control,     1),"  &
    "68  (GEN_1, IOUT(5),     output3, 0,   69,  1,  Z),"  & 
    "69  (GEN_1, *,           control,     1),"  &
    "70  (GEN_1, IOUT(4) ,    output3, 0,   71,  1,  Z),"  & 
    "71  (GEN_1, *,           control,     1),"  &
    "72  (GEN_1, IOUT(3),     output3, 0,   73,  1,  Z),"  & 
    "73  (GEN_1, *,           control,     1),"  &
    "74  (GEN_1, IOUT(2),     output3, 0,   75,  1,  Z),"  & 
    "75  (GEN_1, *,           control,     1),"  &
    "76  (GEN_1, IOUT(1),     output3, 0,   77,  1,  Z),"  & 
    "77  (GEN_1, *,           control,     1),"  &
    "78  (GEN_1, IOUT(0),     output3, 0,   79,  1,  Z),"  &  
    "79  (GEN_1, *,           control,     1),"  &
    "80  (GEN_1, SYNCO,       output2,  X),"  &  
    "81  (GEN_1, FSRD,        output2,  X),"  &  
    "82  (GEN_1, FSRC,        output2,  X),"  &  
    "83  (GEN_1, FSRB,        output2,  X),"  &  
    "84  (GEN_1, FSRA,        output2,  X),"  &  
    "85  (GEN_1, SCLKD,       output2,  X),"  &  
    "86  (GEN_1, SCLKC,       output2,  X),"  &  
    "87  (GEN_1, SCLKB,       output2,  X),"  &  
    "88  (GEN_1, SCLKA,       output2,  X),"  &  
    "89  (GEN_1, SDD,         input,  0),"  &  
    "90  (GEN_1, SDC,         input,  0),"  &  
    "91  (GEN_1, SDB,         input,  0),"  &  
    "92  (GEN_1, SDA,         input,  0),"  &  
    "93  (GEN_1, UPDD,        input,  0),"  &  
    "94  (GEN_1, UPDC,        input,  0),"  &  
    "95  (GEN_1, UPDB,        input,  0),"  &  
    "96  (GEN_1, UPDA,        input,  0),"  &  
    "97  (GEN_1, TXEND,       input,  0),"  &  
    "98  (GEN_1, TXENC,       input,  0),"  &  
    "99  (GEN_1, TXENB,       input,  0),"  &  
    "100  (GEN_1, TXENA,      input,  0),"  &  
    "101  (GEN_1, QIN(19),    bidir,    0,    102,     1,      Z),"  &
    "102  (GEN_1, *,          control,  1),"  &
    "103  (GEN_1, QIN(18),    bidir,    0,    104,     1,      Z),"  &
    "104  (GEN_1, *,          control,  1),"  &
    "105  (GEN_1, QIN(17),    bidir,    0,    106,     1,      Z),"  &
    "106  (GEN_1, *,          control,  1),"  &
    "107  (GEN_1, QIN(16),    bidir,    0,    108,     1,      Z),"  &
    "108  (GEN_1, *,          control,  1),"  &
    "109  (GEN_1, QIN(15),    bidir,    0,    110,     1,      Z),"  &
    "110  (GEN_1, *,          control,  1),"  &
    "111  (GEN_1, QIN(14),    bidir,    0,    112,     1,      Z),"  &
    "112  (GEN_1, *,          control,  1),"  &
    "113  (GEN_1, QIN(13),    bidir,    0,    114,     1,      Z),"  &
    "114  (GEN_1, *,          control,  1),"  &
    "115  (GEN_1, QIN(12),    bidir,    0,    116,     1,      Z),"  &
    "116  (GEN_1, *,          control,  1),"  &
    "117  (GEN_1, QIN(11),    bidir,    0,    118,     1,      Z),"  &
    "118  (GEN_1, *,          control,  1),"  &
    "119  (GEN_1, QIN(10),    bidir,    0,    120,     1,      Z),"  &
    "120  (GEN_1, *,          control,  1),"  &
    "121  (GEN_1, QIN(9),     bidir,    0,    122,     1,      Z),"  &
    "122  (GEN_1, *,          control,  1),"  &
    "123  (GEN_1, QIN(8),     bidir,    0,    124,     1,      Z),"  &
    "124  (GEN_1, *,          control,  1),"  &
    "125  (GEN_1, QIN(7),     bidir,    0,    126,     1,      Z),"  &
    "126  (GEN_1, *,          control,  1),"  &
    "127  (GEN_1, QIN(6),     bidir,    0,    128,     1,      Z),"  &
    "128  (GEN_1, *,          control,  1),"  &
    "129  (GEN_1, QIN(5),     bidir,    0,    130,     1,      Z),"  &
    "130  (GEN_1, *,          control,  1),"  &
    "131  (GEN_1, QIN(4),     bidir,    0,    132,     1,      Z),"  &
    "132  (GEN_1, *,          control,  1),"  &
    "133  (GEN_1, QIN(3),     bidir,    0,    134,     1,      Z),"  &
    "134  (GEN_1, *,          control,  1),"  &
    "135  (GEN_1, QIN(2),     bidir,    0,    136,     1,      Z),"  &
    "136  (GEN_1, *,          control,  1),"  &
    "137  (GEN_1, QIN(1),     bidir,    0,    138,     1,      Z),"  &
    "138  (GEN_1, *,          control,  1),"  &
    "139  (GEN_1, QIN(0),     bidir,    0,    140,     1,      Z),"  &
    "140  (GEN_1, *,          control,  1),"  &
    "141  (GEN_1, IIN(19),    bidir,    0,    142,     1,      Z),"  &
    "142  (GEN_1, *,          control,  1),"  &
    "143  (GEN_1, IIN(18),    bidir,    0,    144,     1,      Z),"  &
    "144  (GEN_1, *,          control,  1),"  &
    "145  (GEN_1, IIN(17),    bidir,    0,    146,     1,      Z),"  &
    "146  (GEN_1, *,          control,  1),"  &
    "147  (GEN_1, IIN(16),    bidir,    0,    148,     1,      Z),"  &
    "148  (GEN_1, *,          control,  1),"  &
    "149  (GEN_1, IIN(15),    bidir,    0,    150,     1,      Z),"  &
    "150  (GEN_1, *,          control,  1),"  &
    "151  (GEN_1, IIN(14),    bidir,    0,    152,     1,      Z),"  &
    "152  (GEN_1, *,          control,  1),"  &
    "153  (GEN_1, IIN(13),    bidir,    0,    154,     1,      Z),"  &
    "154  (GEN_1, *,          control,  1),"  &
    "155  (GEN_1, IIN(12),    bidir,    0,    156,     1,      Z),"  &
    "156  (GEN_1, *,          control,  1),"  &
    "157  (GEN_1, IIN(11),    bidir,    0,    158,     1,      Z),"  &
    "158  (GEN_1, *,          control,  1),"  &
    "159  (GEN_1, IIN(10),    bidir,    0,    160,     1,      Z),"  &
    "160  (GEN_1, *,          control,  1),"  &
    "161  (GEN_1, IIN(9),     bidir,    0,    162,     1,      Z),"  &
    "162  (GEN_1, *,          control,  1),"  &
    "163  (GEN_1, IIN(8),     bidir,    0,    164,     1,      Z),"  &
    "164  (GEN_1, *,          control,  1),"  &
    "165  (GEN_1, IIN(7),     bidir,    0,    166,     1,      Z),"  &
    "166  (GEN_1, *,          control,  1),"  &
    "167  (GEN_1, IIN(6),     bidir,    0,    168,     1,      Z),"  &
    "168  (GEN_1, *,          control,  1),"  &
    "169  (GEN_1, IIN(5),     bidir,    0,    170,     1,      Z),"  &
    "170  (GEN_1, *,          control,  1),"  &
    "171  (GEN_1, IIN(4),     bidir,    0,    172,     1,      Z),"  &
    "172  (GEN_1, *,          control,  1),"  &
    "173  (GEN_1, IIN(3),     bidir,    0,    174,     1,      Z),"  &
    "174  (GEN_1, *,          control,  1),"  &
    "175  (GEN_1, IIN(2),     bidir,    0,    176,     1,      Z),"  &
    "176  (GEN_1, *,          control,  1),"  &
    "177  (GEN_1, IIN(1),     bidir,    0,    178,     1,      Z),"  &
    "178  (GEN_1, *,          control,  1),"  &
    "179  (GEN_1, IIN(0),     bidir,    0,    180,     1,      Z),"  &
    "180  (GEN_1, *,          control,  1),"  &
    "181  (GEN_1, P(15),      bidir,    0,    182,     1,      Z),"  &
    "182  (GEN_1, *,          control,  1),"  &
    "183  (GEN_1, P(14),      bidir,    0,    184,     1,      Z),"  &
    "184  (GEN_1, *,          control,  1),"  &
    "185  (GEN_1, P(13),      bidir,    0,    186,     1,      Z),"  &
    "186  (GEN_1, *,          control,  1),"  &
    "187  (GEN_1, P(12),      bidir,    0,    188,     1,      Z),"  &
    "188  (GEN_1, *,          control,  1),"  &
    "189 (GEN_1, P(11),       bidir,    0,    190,    1,      Z),"  &
    "190 (GEN_1, *,           control,  1),"  &
    "191 (GEN_1, P(10),       bidir,    0,    192,    1,      Z),"  &
    "192 (GEN_1, *,           control,  1),"  &
    "193 (GEN_1, P(9),        bidir,    0,    194,    1,      Z),"  &
    "194 (GEN_1, *,           control,  1),"  &
    "195 (GEN_1, P(8),        bidir,    0,    196,    1,      Z),"  &
    "196 (GEN_1, *,           control,  1),"  &
    "197 (GEN_1, P(7),        bidir,    0,    198,    1,      Z),"  &
    "198 (GEN_1, *,           control,  1),"  &
    "199 (GEN_1, P(6),        bidir,    0,    200,    1,      Z),"  &
    "200 (GEN_1, *,           control,  1),"  &
    "201 (GEN_1, P(5),        bidir,    0,    202,    1,      Z),"  &
    "202 (GEN_1, *,           control,  1),"  &
    "203 (GEN_1, P(4),        bidir,    0,    204,    1,      Z),"  &
    "204 (GEN_1, *,           control,  1),"  &
    "205 (GEN_1, P(3),        bidir,    0,    206,    1,      Z),"  &
    "206 (GEN_1, *,           control,  1),"  &
    "207 (GEN_1, P(2),        bidir,    0,    208,    1,      Z),"  &
    "208 (GEN_1, *,           control,  1),"  &
    "209 (GEN_1, P(1),        bidir,    0,    210,    1,      Z),"  &
    "210 (GEN_1, *,           control,  1),"  &
    "211 (GEN_1, P(0),        bidir,    0,    212,    1,      Z),"  &
    "212 (GEN_1, *,           control,  1),"  &
    "213 (GEN_1, RD,          input,    1),"  &
    "214 (GEN_1, WR,          input,    0),"  &
    "215 (GEN_1, A(6),        input,    0),"  &
    "216 (GEN_1, A(5),        input,    0),"  &
    "217 (GEN_1, A(4),        input,    0),"  &
    "218 (GEN_1, A(3),        input,    0),"  &
    "219 (GEN_1, A(2),        input,    0),"  &
    "220 (GEN_1, A(1),        input,    0),"  &
    "221 (GEN_1, A(0),        input,    0),"  &
    "222 (GEN_1, CS,          input,    0),"  &
    "223 (GEN_1, OUTEN1,      input,    1),"  &
    "224 (GEN_1, OUTEN0,      input,    1),"  &
    "225 (GEN_1, TRITST,      input,    0),"  &
    "226 (GEN_1, OFFBIN,      input,    0),"  &
    "227 (GEN_1, ISTRB,       output2,    0),"  &
    "228 (GEN_1, RDMODE,      input,    0),"  &
    "229 (GEN_1, RESET,       input,    1),"  &
    "230 (GEN_1, CLK,         input,    0)"  ;
     
end ISL5217;

This library contains 7714 BSDL files (for 6086 distinct entities) from 64 vendors
Last BSDL model (CY7C1512KV18) was added on Sep 15, 2017 14:30
info@bsdl.info