-- **********************************************************************
--
-- FILE : zl38005gg.bsd
-- generated by Cz.Piasta as zl38005 on Fri Jul 6 14:54:32 EDT 2007
-- using p.jtag.bsd rev 3.5 - 9 May, 2007
--
-- BSDL description for top level entity zl38005
-- Device : ZL38005 Voice Processor Dual with NarrowBand Codecs
-- Package : 96-Pin CABGA
--
-- Number of BSC cells: 65
--
-- **********************************************************************
-- Modification History:
-- Initial release: Fri Jul 6 14:54:32 EDT 2007
-- **********************************************************************
--
-- IMPORTANT NOTICE
--
-- This information is for modeling purposes only, and is not guaranteed.
--
-- This information is provided "as is" without warranty of any kind.
-- It may contain technical inaccuracies or typographical errors.
--
-- ZARLINK and ZL38005 are trademarks of ZARLINK Semiconductor. ZARLINK
-- products, marketed under trademarks, are protected under numerous US
-- and foreign patents and pending applications, maskwork rights, and
-- copyrights.
--
-- ZARLINK reserves the right to make changes to any products and
-- services at any time without notice. ZARLINK assumes no
-- responsibility or liability arising out of the application or use of
-- any information, product, or service described herein except as
-- expressly agreed to in writing by ZARLINK Corporation. ZARLINK
-- customers are advised to obtain the latest version of device
-- specifications before relying on any published information and before
-- placing orders for products or services.
--
-- ======================================================================
-- This BSDL model has been validated for syntax and semantics compliance
-- to IEEE 1149.1 using ASSET/Agilent BSDL Validation Service.
-- ======================================================================
--
-- ********************************************************************
--
-- SPECIAL NOTES
--
-- 1. All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
-- 2. IC_GND - tie low for normal operation
--
-- 3. IC_OPEN1, IC_OPEN2 - Internal Connect. Leave open for normal operation.
--
-- ********************************************************************
entity zl38005 is
generic(PHYSICAL_PIN_MAP : string := "LFBGA_PACKAGE");
port (
AGUARD: linkage bit;
BIAS_RF_M: linkage bit;
BIAS_RF_P: linkage bit;
BIAS_VCM: linkage bit;
C0_ADCI_M: linkage bit;
C0_ADCI_P: linkage bit;
C0_BFO_M: linkage bit;
C0_BFO_P: linkage bit;
C0_DACO_M: linkage bit;
C0_DACO_P: linkage bit;
C1_ADCI_M: linkage bit;
C1_ADCI_P: linkage bit;
C1_BFO_M: linkage bit;
C1_BFO_P: linkage bit;
C1_DACO_M: linkage bit;
C1_DACO_P: linkage bit;
DGUARD: linkage bit;
GPIO: inout bit_vector (0 to 10);
I2S_LRCK: inout bit;
I2S_MCLK: inout bit;
I2S_SCK: inout bit;
I2S_SD_IO: inout bit;
I2S_SDI: in bit;
IC_GND: linkage bit;
IC_OPEN1: linkage bit;
IC_OPEN2: linkage bit;
NC: linkage bit_vector (1 to 9);
OSCI: linkage bit;
OSCO: linkage bit;
PCM_CLKI: in bit;
PCM_CLKO: out bit;
PCM_LBCI: in bit;
PENA2: inout bit;
PFPB_PENA1: inout bit;
PPCMI: in bit;
PPCMO: out bit;
RST_B: in bit;
SPIM_CLK: out bit;
SPIM_CS_B0: out bit;
SPIM_CS_B1: out bit;
SPIM_MISO: in bit;
SPIM_MOSI: out bit;
SPIS_CLK: in bit;
SPIS_CS_B: in bit;
SPIS_MISO: out bit;
SPIS_MOSI: in bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
TRST_B: in bit;
UART_RX: in bit;
UART_TX: out bit;
AVDD_APLL: linkage bit;
AVSS_APLL: linkage bit;
C0_AVDD: linkage bit;
C0_AVSS: linkage bit;
C1_AVDD: linkage bit;
C1_AVSS: linkage bit;
DVDD_APLL: linkage bit;
DVSS_APLL: linkage bit;
VDD_CORE: linkage bit_vector (1 to 3);
VDD_DPLL: linkage bit;
VDD_IO: linkage bit_vector (1 to 3);
VDD_OSC: linkage bit;
VDD_OSC_IO: linkage bit;
VSS_CORE: linkage bit_vector (1 to 3);
VSS_DPLL: linkage bit;
VSS_IO: linkage bit_vector (1 to 3);
VSS_OSC: linkage bit
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of zl38005 : entity is
"STD_1149_1_2001";
attribute PIN_MAP of zl38005 : entity is PHYSICAL_PIN_MAP;
constant LFBGA_PACKAGE : PIN_MAP_STRING :=
"AGUARD : C7 , " &
"BIAS_RF_M : A6 , " &
"BIAS_RF_P : B6 , " &
"BIAS_VCM : C6 , " &
"C0_ADCI_M : A8 , " &
"C0_ADCI_P : A7 , " &
"C0_BFO_M : B7 , " &
"C0_BFO_P : B8 , " &
"C0_DACO_M : A10 , " &
"C0_DACO_P : A11 , " &
"C1_ADCI_M : A4 , " &
"C1_ADCI_P : A5 , " &
"C1_BFO_M : B5 , " &
"C1_BFO_P : B4 , " &
"C1_DACO_M : A2 , " &
"C1_DACO_P : A1 , " &
"DGUARD : D3 , " &
"GPIO :(J2 , " & -- GPIO[0]
"K1 , " & -- GPIO[1]
"K2 , " & -- GPIO[2]
"L1 , " & -- GPIO[3]
"L2 , " & -- GPIO[4]
"K3 , " & -- GPIO[5]
"L3 , " & -- GPIO[6]
"K10 , " & -- GPIO[7]
"L9 , " & -- GPIO[8]
"L10 , " & -- GPIO[9]
"L11 ), " & -- GPIO[10]
"I2S_LRCK : H1 , " &
"I2S_MCLK : G2 , " &
"I2S_SCK : G1 , " &
"I2S_SD_IO : H2 , " &
"I2S_SDI : J1 , " &
"IC_GND : E2 , " &
"IC_OPEN1 : C4 , " &
"IC_OPEN2 : C5 , " &
"NC :(B2 , " & -- NC[1]
"C3 , " & -- NC[2]
"C8 , " & -- NC[3]
"G9 , " & -- NC[4]
"H9 , " & -- NC[5]
"J3 , " & -- NC[6]
"J4 , " & -- NC[7]
"J8 , " & -- NC[8]
"J9 ), " & -- NC[9]
"OSCI : C11 , " &
"OSCO : D11 , " &
"PCM_CLKI : E11 , " &
"PCM_CLKO : J11 , " &
"PCM_LBCI : E10 , " &
"PENA2 : K11 , " &
"PFPB_PENA1 : G11 , " &
"PPCMI : F11 , " &
"PPCMO : H11 , " &
"RST_B : D2 , " &
"SPIM_CLK : L6 , " &
"SPIM_CS_B0 : L7 , " &
"SPIM_CS_B1 : K8 , " &
"SPIM_MISO : L8 , " &
"SPIM_MOSI : K7 , " &
"SPIS_CLK : L5 , " &
"SPIS_CS_B : L4 , " &
"SPIS_MISO : K5 , " &
"SPIS_MOSI : K4 , " &
"TCK : D1 , " &
"TDI : C1 , " &
"TDO : E1 , " &
"TMS : C2 , " &
"TRST_B : B1 , " &
"UART_RX : F2 , " &
"UART_TX : F1 , " &
"AVDD_APLL : B11 , " &
"AVSS_APLL : C10 , " &
"C0_AVDD : A9 , " &
"C0_AVSS : B9 , " &
"C1_AVDD : A3 , " &
"C1_AVSS : B3 , " &
"DVDD_APLL : B10 , " &
"DVSS_APLL : C9 , " &
"VDD_CORE :(G3, J7, G10)," &
"VDD_DPLL : F10 , " &
"VDD_IO :(H3, J5, K9)," &
"VDD_OSC : F9 , " &
"VDD_OSC_IO : D10 , " &
"VSS_CORE :(E3, K6, H10)," &
"VSS_DPLL : E9 , " &
"VSS_IO :(F3, J6, J10)," &
"VSS_OSC : D9";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6,BOTH);
attribute TAP_SCAN_RESET of TRST_B : signal is true;
--
-- NOTE: All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
attribute INSTRUCTION_LENGTH of zl38005 : entity is 17;
attribute INSTRUCTION_OPCODE of zl38005 : entity is
"bypass (00000000000000000)," &
"bypass (11111111111111111)," &
"clamp (11111111111101111)," &
"extest (11111111111101000)," &
"highz (11111111111001111)," &
"idcode (11111111111111110)," &
"preload (11111111111111000)," &
"sample (11111111111111000)";
attribute INSTRUCTION_CAPTURE of zl38005 : entity is "xxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of zl38005 : entity is
"0001" & -- version
"1001010001110101" & -- part number
"00010100101" & -- manufacturer id
"1";
attribute REGISTER_ACCESS of zl38005 : entity is
"boundary (extest, sample, preload)," &
"bypass (bypass, clamp, highz)," &
"device_id (idcode)" ;
attribute BOUNDARY_LENGTH of zl38005 : entity is 65;
attribute BOUNDARY_REGISTER of zl38005 : entity is
-- num cell port function safe ccel disval rslt
" 0 ( BC_0, *, internal, X) ," &
" 1 ( BC_4, RST_B, input, X) ," &
" 2 ( BC_4, UART_RX, input, X) ," &
" 3 ( BC_2, UART_TX, output3, X, 4, 1, Z) ," &
" 4 ( BC_2, *, control, 1) ," &
" 5 ( BC_7, I2S_SCK, bidir, X, 6, 1, Z) ," &
" 6 ( BC_2, *, control, 1) ," &
" 7 ( BC_7, I2S_MCLK, bidir, X, 8, 1, Z) ," &
" 8 ( BC_2, *, control, 1) ," &
" 9 ( BC_0, *, internal, X) ," &
" 10 ( BC_7, I2S_LRCK, bidir, X, 11, 1, Z) ," &
" 11 ( BC_2, *, control, 1) ," &
" 12 ( BC_7, I2S_SD_IO, bidir, X, 13, 1, Z) ," &
" 13 ( BC_2, *, control, 1) ," &
" 14 ( BC_4, I2S_SDI, input, X) ," &
" 15 ( BC_7, GPIO(0), bidir, X, 16, 1, Z) ," &
" 16 ( BC_2, *, control, 1) ," &
" 17 ( BC_7, GPIO(1), bidir, X, 18, 1, Z) ," &
" 18 ( BC_2, *, control, 1) ," &
" 19 ( BC_7, GPIO(2), bidir, X, 20, 1, Z) ," &
" 20 ( BC_2, *, control, 1) ," &
" 21 ( BC_7, GPIO(3), bidir, X, 22, 1, Z) ," &
" 22 ( BC_2, *, control, 1) ," &
" 23 ( BC_7, GPIO(4), bidir, X, 24, 1, Z) ," &
" 24 ( BC_2, *, control, 1) ," &
" 25 ( BC_7, GPIO(5), bidir, X, 26, 1, Z) ," &
" 26 ( BC_2, *, control, 1) ," &
" 27 ( BC_7, GPIO(6), bidir, X, 28, 1, Z) ," &
" 28 ( BC_2, *, control, 1) ," &
" 29 ( BC_4, SPIS_MOSI, input, X) ," &
" 30 ( BC_4, SPIS_CS_B, input, X) ," &
" 31 ( BC_2, SPIS_MISO, output3, X, 32, 1, Z) ," &
" 32 ( BC_2, *, control, 1) ," &
" 33 ( BC_4, SPIS_CLK, input, X) ," &
" 34 ( BC_0, *, internal, X) ," &
" 35 ( BC_2, SPIM_CLK, output3, X, 36, 1, Z) ," &
" 36 ( BC_2, *, control, 1) ," &
" 37 ( BC_2, SPIM_MOSI, output3, X, 38, 1, Z) ," &
" 38 ( BC_2, *, control, 1) ," &
" 39 ( BC_0, *, internal, X) ," &
" 40 ( BC_2, SPIM_CS_B0, output3, X, 41, 1, Z) ," &
" 41 ( BC_2, *, control, 1) ," &
" 42 ( BC_2, SPIM_CS_B1, output3, X, 43, 1, Z) ," &
" 43 ( BC_2, *, control, 1) ," &
" 44 ( BC_4, SPIM_MISO, input, X) ," &
" 45 ( BC_7, GPIO(7), bidir, X, 46, 1, Z) ," &
" 46 ( BC_2, *, control, 1) ," &
" 47 ( BC_7, GPIO(8), bidir, X, 48, 1, Z) ," &
" 48 ( BC_2, *, control, 1) ," &
" 49 ( BC_7, GPIO(9), bidir, X, 50, 1, Z) ," &
" 50 ( BC_2, *, control, 1) ," &
" 51 ( BC_7, GPIO(10), bidir, X, 52, 1, Z) ," &
" 52 ( BC_2, *, control, 1) ," &
" 53 ( BC_7, PENA2, bidir, X, 54, 1, Z) ," &
" 54 ( BC_2, *, control, 1) ," &
" 55 ( BC_0, *, internal, X) ," &
" 56 ( BC_2, PCM_CLKO, output3, X, 57, 1, Z) ," &
" 57 ( BC_2, *, control, 1) ," &
" 58 ( BC_2, PPCMO, output3, X, 59, 1, Z) ," &
" 59 ( BC_2, *, control, 1) ," &
" 60 ( BC_7, PFPB_PENA1, bidir, X, 61, 1, Z) ," &
" 61 ( BC_2, *, control, 1) ," &
" 62 ( BC_4, PPCMI, input, X) ," &
" 63 ( BC_4, PCM_LBCI, input, X) ," &
" 64 ( BC_4, PCM_CLKI, input, X) ";
end zl38005;
------------- end of BSDL description for the zl38005 ----------