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ChipVORX ISP IP for Ultra Fast Flash Programming
BSDL File: dp83867pap Download View details  


-------------------------------------------------------------------------------
-- 
--   (C) Copyright Cadence Design Systems, Inc.
-- 
--   BSDL generated by RTL Compiler v11.20-s006_1
--   Created on: Tue Jul 22 23:51:20 2014 
-- 
--   This BSDL is suitable for Cadence Test 1149.1 BSV (it includes the necessary PORT_ALIAS statement for vectored port names).
-- 
-------------------------------------------------------------------------------

entity dp83867pap is
-- Entity declaration

generic (PHYSICAL_PIN_MAP : string := "dummy");

port (
     led0 : inout bit;
     led1 : inout bit;
     led2 : inout bit;
     mdint_pwdn : inout bit;
     reset_n : in bit;
     cs_gpio_2 : inout bit;
     col_gpio_1 : inout bit;
     rx_err_gpio_0 : inout bit;
     rx_dv_ctl : inout bit;
     tx_en_ctl : inout bit;
     rxd7 : inout bit;
     rxd6 : inout bit;
     rxd5 : inout bit;
     rxd4 : inout bit;
     rxd3 : inout bit;
     rxd2 : inout bit;
     rxd1 : inout bit;
     rxd0 : inout bit;
     rx_clk : inout bit;
     gtx_clk : in bit;
     tx_err : inout bit;
     txd0 : inout bit;
     txd1 : inout bit;
     txd2 : inout bit;
     txd3 : inout bit;
     txd4 : inout bit;
     txd5 : inout bit;
     txd6 : inout bit;
     txd7 : inout bit;
     tx_clk : inout bit;
     jtdi : in bit;
     jtms : in bit;
     jtdo : out bit;
     jtck : in bit;
     jtrst : in bit;
     clk_o : inout bit;
     mdio : inout bit;
     mdc : in bit;
     xi : linkage bit;
     xo : linkage bit;
     atp3 : linkage bit;
     rbias : linkage bit;
     tdmd : linkage bit;
     tdpd : linkage bit;
     tdmc : linkage bit;
     tdpc : linkage bit;
     atp2 : linkage bit;
     atp1 : linkage bit;
     tdmb : linkage bit;
     tdpb : linkage bit;
     tdma : linkage bit;
     tdpa : linkage bit;
     atp0 : linkage bit;
     P_VDDIO : linkage bit_vector(0 to 2);
     P_VDDA2P5 : linkage bit_vector(0 to 1);
     P_VDDA_1P8V_CD : linkage bit;
     P_VDDA_1P8V_AB : linkage bit;
     P_VDD1P1 : linkage bit_vector(0 to 3)
     );

use STD_1149_1_2001.all ;
use CDNDFT_1149_1_2001.all ;

attribute COMPONENT_CONFORMANCE of dp83867pap: entity is "STD_1149_1_2001";

attribute PIN_MAP of dp83867pap : entity is PHYSICAL_PIN_MAP;

constant dummy : PIN_MAP_STRING :=
                                "led0:63, " &
                                "led1:62, " &
                                "led2:61, " &
                                "mdint_pwdn:60, " &
                                "reset_n:59, " &
                                "cs_gpio_2:56, " &
                                "col_gpio_1:55, " &
                                "rx_err_gpio_0:54, " &
                                "rx_dv_ctl:53, " &
                                "tx_en_ctl:52, " &
                                "rxd7:51, " &
                                "rxd6:50, " &
                                "rxd5:49, " &
                                "rxd4:48, " &
                                "rxd3:47, " &
                                "rxd2:46, " &
                                "rxd1:45, " &
                                "rxd0:44, " &
                                "rx_clk:43, " &
                                "gtx_clk:40, " &
                                "tx_err:39, " &
                                "txd0:38, " &
                                "txd1:37, " &
                                "txd2:36, " &
                                "txd3:35, " &
                                "txd4:34, " &
                                "txd5:33, " &
                                "txd6:32, " &
                                "txd7:31, " &
                                "tx_clk:30, " &
                                "jtdi:28, " &
                                "jtms:27, " &
                                "jtdo:26, " &
                                "jtck:25, " &
                                "jtrst:24, " &
                                "clk_o:22, " &
                                "mdio:21, " &
                                "mdc:20, " &
                                "xi:19, " &
                                "xo:18, " &
                                "atp3:16, " &
                                "rbias:15, " &
                                "tdmd:14, " &
                                "tdpd:13, " &
                                "tdmc:11, " &
                                "tdpc:10, " &
                                "atp2:9, " &
                                "atp1:7, " &
                                "tdmb:6, " &
                                "tdpb:5, " &
                                "tdma:3, " &
                                "tdpa:2, " &
                                "atp0:1, " &
                                "P_VDDIO:(57, " &
                                "41, " &
                                "23), " &
                                "P_VDDA2P5:(12, " &
                                "4), " &
                                "P_VDDA_1P8V_CD:17, " &
                                "P_VDDA_1P8V_AB:64, " &
                                "P_VDD1P1:(58, " &
                                "42, " &
                                "29, " &
                                "8)";

--Scan Port Identification
attribute TAP_SCAN_IN of jtdi: signal is true;
attribute TAP_SCAN_MODE of jtms: signal is true;
attribute TAP_SCAN_OUT of jtdo: signal is true;
attribute TAP_SCAN_CLOCK of jtck: signal is (20.0e6, BOTH);
attribute TAP_SCAN_RESET of jtrst: signal is true;

attribute INSTRUCTION_LENGTH of dp83867pap: entity is 3;

attribute INSTRUCTION_OPCODE of dp83867pap: entity is
     "BYPASS         (111)," &
     "EXTEST         (001)," &
     "SAMPLE         (010)," &
     "PRELOAD        (010)," &
     "TESTMODE_REG   (100)" ; 

attribute INSTRUCTION_CAPTURE of dp83867pap: entity is "x01";   -- req'd by Std.

attribute INSTRUCTION_PRIVATE of dp83867pap: entity is "TESTMODE_REG";

attribute REGISTER_ACCESS of dp83867pap : entity is
"BOUNDARY (EXTEST,SAMPLE,PRELOAD)," &
"BYPASS (BYPASS)" ;

attribute BOUNDARY_LENGTH of dp83867pap: entity is 63; 

attribute BOUNDARY_REGISTER of dp83867pap: entity is
"0  (BC_BIDIR, led0, BIDIR, X, 1, 1, Z)," &
"1  (BC_ENAB_NT, *, CONTROL, 1)," &
"2  (BC_BIDIR, led1, BIDIR, X, 3, 1, Z)," &
"3  (BC_ENAB_NT, *, CONTROL, 1)," &
"4  (BC_BIDIR, led2, BIDIR, X, 5, 1, Z)," &
"5  (BC_ENAB_NT, *, CONTROL, 1)," &
"6  (BC_BIDIR, mdint_pwdn, BIDIR, X, 7, 1, WEAK1)," &
"7  (BC_ENAB_NT, *, CONTROL, 1)," &
"8  (BC_IN, reset_n, INPUT, X)," &
"9  (BC_BIDIR, cs_gpio_2, BIDIR, X, 10, 1, Z)," &
"10  (BC_ENAB_NT, *, CONTROL, 1)," &
"11  (BC_BIDIR, col_gpio_1, BIDIR, X, 12, 1, Z)," &
"12  (BC_ENAB_NT, *, CONTROL, 1)," &
"13  (BC_BIDIR, rx_err_gpio_0, BIDIR, X, 14, 1, Z)," &
"14  (BC_ENAB_NT, *, CONTROL, 1)," &
"15  (BC_BIDIR, rx_dv_ctl, BIDIR, X, 16, 1, Z)," &
"16  (BC_ENAB_NT, *, CONTROL, 1)," &
"17  (BC_BIDIR, tx_en_ctl, BIDIR, X, 18, 1, WEAK0)," &
"18  (BC_ENAB_NT, *, CONTROL, 1)," &
"19  (BC_BIDIR, rxd7, BIDIR, X, 20, 1, Z)," &
"20  (BC_ENAB_NT, *, CONTROL, 1)," &
"21  (BC_BIDIR, rxd6, BIDIR, X, 22, 1, Z)," &
"22  (BC_ENAB_NT, *, CONTROL, 1)," &
"23  (BC_BIDIR, rxd5, BIDIR, X, 24, 1, Z)," &
"24  (BC_ENAB_NT, *, CONTROL, 1)," &
"25  (BC_BIDIR, rxd4, BIDIR, X, 26, 1, Z)," &
"26  (BC_ENAB_NT, *, CONTROL, 1)," &
"27  (BC_BIDIR, rxd3, BIDIR, X, 28, 1, Z)," &
"28  (BC_ENAB_NT, *, CONTROL, 1)," &
"29  (BC_BIDIR, rxd2, BIDIR, X, 30, 1, Z)," &
"30  (BC_ENAB_NT, *, CONTROL, 1)," &
"31  (BC_BIDIR, rxd1, BIDIR, X, 32, 1, Z)," &
"32  (BC_ENAB_NT, *, CONTROL, 1)," &
"33  (BC_BIDIR, rxd0, BIDIR, X, 34, 1, Z)," &
"34  (BC_ENAB_NT, *, CONTROL, 1)," &
"35  (BC_BIDIR, rx_clk, BIDIR, X, 36, 1, Z)," &
"36  (BC_ENAB_NT, *, CONTROL, 1)," &
"37  (BC_IN, gtx_clk, INPUT, X)," &
"38  (BC_BIDIR, tx_err, BIDIR, X, 39, 1, WEAK0)," &
"39  (BC_ENAB_NT, *, CONTROL, 1)," &
"40  (BC_BIDIR, txd0, BIDIR, X, 41, 1, WEAK0)," &
"41  (BC_ENAB_NT, *, CONTROL, 1)," &
"42  (BC_BIDIR, txd1, BIDIR, X, 43, 1, WEAK0)," &
"43  (BC_ENAB_NT, *, CONTROL, 1)," &
"44  (BC_BIDIR, txd2, BIDIR, X, 45, 1, WEAK0)," &
"45  (BC_ENAB_NT, *, CONTROL, 1)," &
"46  (BC_BIDIR, txd3, BIDIR, X, 47, 1, WEAK0)," &
"47  (BC_ENAB_NT, *, CONTROL, 1)," &
"48  (BC_BIDIR, txd4, BIDIR, X, 49, 1, WEAK0)," &
"49  (BC_ENAB_NT, *, CONTROL, 1)," &
"50  (BC_BIDIR, txd5, BIDIR, X, 51, 1, WEAK0)," &
"51  (BC_ENAB_NT, *, CONTROL, 1)," &
"52  (BC_BIDIR, txd6, BIDIR, X, 53, 1, WEAK0)," &
"53  (BC_ENAB_NT, *, CONTROL, 1)," &
"54  (BC_BIDIR, txd7, BIDIR, X, 55, 1, WEAK0)," &
"55  (BC_ENAB_NT, *, CONTROL, 1)," &
"56  (BC_BIDIR, tx_clk, BIDIR, X, 57, 1, Z)," &
"57  (BC_ENAB_NT, *, CONTROL, 1)," &
"58  (BC_BIDIR, clk_o, BIDIR, X, 59, 1, Z)," &
"59  (BC_ENAB_NT, *, CONTROL, 1)," &
"60  (BC_BIDIR, mdio, BIDIR, X, 61, 1, Z)," &
"61  (BC_ENAB_NT, *, CONTROL, 1)," &
"62  (BC_IN, mdc, INPUT, X)";

attribute BOUNDARY_SCAN_DESIGN_TYPE: BSDL_EXTENSION;

attribute BOUNDARY_SCAN_DESIGN_TYPE of dp83867pap: entity is "IEEE_11491";

end dp83867pap ;

This library contains 10579 BSDL files (for 7657 distinct entities) from 71 vendors
Last BSDL model (CYCLONE_10_10CX220F780) was added on May 21, 2018 13:01
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