--**************************************************************************
--*
--* File Name: MT54W4MH9JF.BSDL
--* Revision: 1.2
--* Date: December 17, 2002
--* Model: BSDL
--* Simulator: Agilent Technologies
--*
--* Dependencies: None
--*
--* Author: Otto Bennig
--* Email: obennig@micron.com
--* Phone: (208) 368-3836
--* Company: Micron Technology, Inc.
--* Model: MT54W4MH9JF (4 Meg x 9 QDR SRAM 4-Word Burst)
--*
--* Description: Micron 36 meg (4 Meg X 9) QDR SRAM 4-Word Burst
--* BSDL model
--*
--* Limitation: IEEE 1149.1 Serial Boundary Scan (JTAG)
--*
--* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS"
--* WITH NO WARRANTY
--* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
--* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--*
--* Copyright (C) 1998 Micron Semiconductor Products, Inc.
--* All rights reserved
--*
--* Rev Author Phone Date Changes
--* --- -------------- -------------------------- -----------------------
--* 1.1 Otto Bennig 208 368-3836 11/19/2002 Density ID reg changed
--* to reflect 36 meg
--*
--*************************************************************************/
entity MT54W4MH9JF is
generic (PHYSICAL_PIN_MAP : string := "FBGA");
port (
SA: in bit_vector(0 to 19);
CQ_n: buffer bit;
W_n: in bit;
K_n: in bit;
R_n: in bit;
CQ: buffer bit;
K: in bit;
BW0_n: in bit;
C: in bit;
C_n: in bit;
D: in bit_vector (0 to 8);
Q: inout bit_vector (0 to 8);
DLL: in bit;
TMS: in bit;
TDI: in bit;
TCK: in bit;
TDO: out bit;
ZQ: in bit;
VREF: linkage bit_vector(0 to 1);
Vdd: linkage bit_vector(0 to 9);
Vss: linkage bit_vector(0 to 25);
VDDQ: linkage bit_vector(0 to 15);
NC: linkage bit_vector(0 to 57));
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of MT54W4MH9JF : entity is
"STD_1149_1_1993";
attribute PIN_MAP of MT54W4MH9JF : entity is PHYSICAL_PIN_MAP;
constant FBGA:PIN_MAP_STRING:=
" SA: (N6,P7,N7,R7,R8,P8,R9,A10,A9,B8, " &
" C7,C5,B4,A3,R3,R4,P4,P5,N5,R5), " & --Address
" CQ_n: A1, " & --Neg Echo Clock
" W_n: A4, " & --Write
" K_n: A6, " & --Out Negative Clock
" R_n: A8, " & --Read
" CQ: A11, " & --Pos Echo Clock
" K: B6, " & --In Positive Clock
" BW0_n: B7, " & --BYTE WRITE
" C: P6, " & --Out Positive Clock
" C_n: R6, " & --Out Negitive Clock
" Q: (P11,L11,J10,E11,B11,E3,G3,L2,P3), " &
" D: (P10,M11,J11,E10,C11,D2,G2,L3,N2), " &
" TMS: R10, " & --Test Mode Select
" TDI: R11, " & --Test Data-In
" TCK: R2, " & --Test Clock
" TDO: R1, " & --Test Data-Out
" DLL: H1, " & --Clock
" ZQ: H11, " & --Input Impedance Match
" VREF: (H2,H10), " & --HSTL Input Reference Voltage
" VDD: (F5,F7,G5,G7,H5,H7,J5,J7,K5,K7), " &
" VSS: (A2,C4,C8,D4,D5,D6,D7,D8,E5,E6,E7,F6,G6, " &
" H6,J6,K6,L5,L6,L7,M4,M5,M6,M7,M8,N4,N8), " &
" VDDQ: (E4,E8,F4,F8,G4,G8,H3,H4,H8,H9,J4,J8,K4,K8,L4,L8), " &
" NC: (A5,A7,B1,B2,B3,B5,B9,B10,C1,C2,C3,C6,C9,C10,D1, " &
" D3,D9,D10,D11,E1,E2,E9,F1,F2,F3,F9,F10,F11,G1, " &
" G9,G10,G11,J1,J2,J3,J9,K1,K2,K3,K9,K10,K11,L1,L9, " &
" L10,M1,M2,M3,M9,M10,N1,N3,N9,N10,N11,P1,P2,P9) " ;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute INSTRUCTION_LENGTH of MT54W4MH9JF : entity is 3;
attribute INSTRUCTION_OPCODE of MT54W4MH9JF : entity is
"EXTEST (000), " &
"IDCODE (001), " &
"SAMPLEZ (010), " &
"RESERV1 (011), " &
"SAMPLE (100), " & --Sample/Preload
"RESERV2 (101), " &
"RESERV3 (110), " &
"BYPASS (111) " ;
attribute INSTRUCTION_CAPTURE of MT54W4MH9JF : entity is "001";
attribute INSTRUCTION_PRIVATE of MT54W4MH9JF : entity is
"RESERV1, RESERV2 ,RESERV3" ;
attribute IDCODE_REGISTER of MT54W4MH9JF : entity is
"000" & --Reserved for version number
"00010000010101010" & --Device ID
"00000101100" & --MICRON JEDIC ID
"1" ; --ID REGISTER PRESENCE INDICATOR
attribute REGISTER_ACCESS of MT54W4MH9JF : entity is
"BOUNDARY (EXTEST,SAMPLEZ,SAMPLE), " &
"BYPASS (BYPASS) " ;
attribute BOUNDARY_LENGTH of MT54W4MH9JF : entity is 109;
attribute BOUNDARY_REGISTER of MT54W4MH9JF : entity is
"0 (BC_4, C_n, input, X), " &
"1 (BC_4, C, input, X), " &
"2 (BC_4, SA(0), input, X), " &
"3 (BC_4, SA(1), input, X), " &
"4 (BC_4, SA(2), input, X), " &
"5 (BC_4, SA(3), input, X), " &
"6 (BC_4, SA(4), input, X), " &
"7 (BC_4, SA(5), input, X), " &
"8 (BC_4, SA(6), input, X), " &
"9 (BC_7, Q(0), bidir, X, 108, 0, Z), " &
"10 (BC_4, D(0), input, X), " &
"11 (BC_4, *, internal, X), " &
"12 (BC_4, *, internal, X), " &
"13 (BC_4, *, internal, X), " &
"14 (BC_4, *, internal, X), " &
"15 (BC_4, *, internal, X), " &
"16 (BC_4, *, internal, X), " &
"17 (BC_7, Q(1), bidir, X, 108, 0, Z), " &
"18 (BC_4, D(1), input, X), " &
"19 (BC_4, *, internal, X), " &
"20 (BC_4, *, internal, X), " &
"21 (BC_4, *, internal, X), " &
"22 (BC_4, *, internal, X), " &
"23 (BC_4, *, internal, X), " &
"24 (BC_4, *, internal, X), " &
"25 (BC_7, Q(2), bidir, X, 108, 0, Z), " &
"26 (BC_4, D(2), input, X), " &
"27 (BC_4, ZQ, input, X), " &
"28 (BC_4, *, internal, X), " &
"29 (BC_4, *, internal, X), " &
"30 (BC_4, *, internal, X), " &
"31 (BC_4, *, internal, X), " &
"32 (BC_4, *, internal, X), " &
"33 (BC_4, *, internal, X), " &
"34 (BC_7, Q(3), bidir, X, 108, 0, Z), " &
"35 (BC_4, D(3), input, X), " &
"36 (BC_4, *, internal, X), " &
"37 (BC_4, *, internal, X), " &
"38 (BC_4, *, internal, X), " &
"39 (BC_4, *, internal, X), " &
"40 (BC_4, *, internal, X), " &
"41 (BC_4, *, internal, X), " &
"42 (BC_7, Q(4), bidir, X, 108, 0, Z), " &
"43 (BC_4, D(4), input, X), " &
"44 (BC_4, *, internal, X), " &
"45 (BC_4, *, internal, X), " &
"46 (BC_9, CQ, output2, X), " &
"47 (BC_4, SA(7), input, X), " &
"48 (BC_4, SA(8), input, X), " &
"49 (BC_4, SA(9), input, X), " &
"50 (BC_4, SA(10), input, X), " &
"51 (BC_4, *, internal, X), " &
"52 (BC_4, R_n, input, X), " &
"53 (BC_4, *, internal, X), " &
"54 (BC_4, BW0_n, input, X), " &
"55 (BC_4, K, input, X), " &
"56 (BC_4, K_n, input, X), " &
"57 (BC_4, *, internal, X), " &
"58 (BC_4, *, internal, X), " &
"59 (BC_4, W_n, input, X), " &
"60 (BC_4, SA(11), input, X), " &
"61 (BC_4, SA(12), input, X), " &
"62 (BC_4, SA(13), input, X), " &
"63 (BC_4, *, internal, X), " &
"64 (BC_9, CQ_n, output2, X), " &
"65 (BC_4, *, internal, X), " &
"66 (BC_4, *, internal, X), " &
"67 (BC_4, *, internal, X), " &
"68 (BC_4, *, internal, X), " &
"69 (BC_4, *, internal, X), " &
"70 (BC_4, *, internal, X), " &
"71 (BC_4, *, internal, X), " &
"72 (BC_4, *, internal, X), " &
"73 (BC_7, Q(5), bidir, X, 108, 0, Z), " &
"74 (BC_4, D(5), input, X), " &
"75 (BC_4, *, internal, X), " &
"76 (BC_4, *, internal, X), " &
"77 (BC_4, *, internal, X), " &
"78 (BC_4, *, internal, X), " &
"79 (BC_4, *, internal, X), " &
"80 (BC_4, *, internal, X), " &
"81 (BC_7, Q(6), bidir, X, 108, 0, Z), " &
"82 (BC_4, D(6), input, X), " &
"83 (BC_4, DLL, input, X), " &
"84 (BC_4, *, internal, X), " &
"85 (BC_4, *, internal, X), " &
"86 (BC_4, *, internal, X), " &
"87 (BC_4, *, internal, X), " &
"88 (BC_4, *, internal, X), " &
"89 (BC_4, *, internal, X), " &
"90 (BC_7, Q(7), bidir, X, 108, 0, Z), " &
"91 (BC_4, D(7), input, X), " &
"92 (BC_4, *, internal, X), " &
"93 (BC_4, *, internal, X), " &
"94 (BC_4, *, internal, X), " &
"95 (BC_4, *, internal, X), " &
"96 (BC_4, *, internal, X), " &
"97 (BC_4, *, internal, X), " &
"98 (BC_7, Q(8), bidir, X, 108, 0, Z), " &
"99 (BC_4, D(8), input, X), " &
"100 (BC_4, *, internal, X), " &
"101 (BC_4, *, internal, X), " &
"102 (BC_4, SA(14), input, X), " &
"103 (BC_4, SA(15), input, X), " &
"104 (BC_4, SA(16), input, X), " &
"105 (BC_4, SA(17), input, X), " &
"106 (BC_4, SA(18), input, X), " &
"107 (BC_4, SA(19), input, X), " &
"108 (BC_2, *, controlr, 0) " ;
end MT54W4MH9JF;