-- M O T O R O L A S S D T J T A G S O F T W A R E
-- BSDL File Generated: Mon Dec 8 16:01:13 1997
--
-- Revision History:
--
entity MC68040VRC is
generic (PHYSICAL_PIN_MAP : string := "PGA_18X18");
port (TDI: in bit;
TDO: out bit;
TMS: in bit;
TCK: in bit;
RSTO: buffer bit;
IPEND: buffer bit;
CIOUT: out bit;
UPA: out bit_vector(0 to 1);
TT: inout bit_vector(0 to 1);
A: inout bit_vector(0 to 31);
D: inout bit_vector(0 to 31);
LOCKE: out bit;
LOCK: out bit;
R_W: inout bit;
TLN: out bit_vector(0 to 1);
TM: out bit_vector(0 to 2);
SIZ: inout bit_vector(0 to 1);
MI: buffer bit;
BR: buffer bit;
TS: inout bit;
BB: inout bit;
TIP: out bit;
PST: buffer bit_vector(0 to 3);
TA: inout bit;
TEA: in bit;
BG: in bit;
SC: in bit_vector(0 to 1);
TBI: in bit;
AVEC: in bit;
TCI: in bit;
TYLO2: in bit;
TYLO3: in bit;
BCLK: in bit;
IPL: in bit_vector(0 to 2);
RSTI: in bit;
CDIS: in bit;
MDIS: in bit;
LOC: inout bit;
LFO: in bit;
SCD: buffer bit;
JTAG: in bit;
GND: linkage bit_vector(1 to 38);
N_C: linkage bit_vector(1 to 2);
VDD: linkage bit_vector(1 to 27));
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of MC68040VRC : entity is "STD_1149_1_1993";
attribute PIN_MAP of MC68040VRC : entity is PHYSICAL_PIN_MAP;
constant PGA_18X18 : PIN_MAP_STRING :=
"A: (L18, K18, J17, J18, H18, G18, G16, F18, E18, F16, P1, N3, N1, M1, L1, K1, K2, " &
"J1, H1, J2, G1, F1, E1, G3, D1, F3, E2, C1, E3, B1, D3, A1), " &
"D: (C3, B3, C4, A2, A3, A4, A5, A6, B7, A7, A8, A9, A10, A11, A12, A13, B11, A14, " &
"B12, A15, A16, A17, B16, C15, A18, C16, B18, D16, C18, E16, E17, D18), " &
"GND: (R4, R6, R10, R11, R13, S15, S17, Q17, M16, N17, L17, K16, H17, F17, D17, B17, " &
"C13, B15, B13, C11, B10, B8, C9, B6, C7, C6, B2, D2, F2, H2, K3, L2, B4, N2, L3, Q2, " &
"S2, S9), " &
"VDD: (R5, R8, R12, S16, R17, L16, M17, G17, C17, C14, C12, S8, B14, C10, B9, C8, B5, " &
"C5, C2, J16, H3, G2, M2, M3, R2, J3, H16), " &
"LFO: D4, " &
"LOC: K4, " &
"TM: (N18, M18, K17), " &
"SCD: M4, " &
"R_W: N16, " &
"TT: (P3, P2), " &
"SIZ: (P17, P16), " &
"TLN: (Q18, P18), " &
"UPA: (Q3, Q1), " &
"MI: Q16, " &
"CIOUT: R1, " &
"RSTO: R3, " &
"BCLK: R7, " &
"TYLO3: R9, " &
"PST: (T15, S14, R14, T16), " &
"TIP: R15, " &
"TS: R16, " &
"LOCKE: R18, " &
"IPEND: S1, " &
"TDI: S3, " &
"TCK: S4, " &
"TMS: S5, " &
"MDIS: S6, " &
"RSTI: S7, " &
"TYLO2: S10, " &
"TBI: S11, " &
"SC: (T12, S12), " &
"TEA: S13, " &
"LOCK: S18, " &
"TDO: T2, " &
"N_C: (T9, T3), " &
"JTAG: T4, " &
"CDIS: T5, " &
"IPL: (T8, T7, T6), " &
"TCI: T10, " &
"AVEC: T11, " &
"BG: T13, " &
"TA: T14, " &
"BB: T17, " &
"BR: T18 ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute COMPLIANCE_PATTERNS of MC68040VRC : entity is
"(JTAG) (0)";
attribute INSTRUCTION_LENGTH of MC68040VRC : entity is 3;
attribute INSTRUCTION_OPCODE of MC68040VRC : entity is
"EXTEST (000)," &
"SAMPLE (010)," &
"CLAMP (100)," &
"HIGHZ (001)," &
"PRIVATE (110)," &
"BYPASS (111)";
attribute INSTRUCTION_CAPTURE of MC68040VRC : entity is "001";
attribute INSTRUCTION_PRIVATE of MC68040VRC : entity is
"PRIVATE ";
attribute BOUNDARY_LENGTH of MC68040VRC : entity is 190;
attribute BOUNDARY_REGISTER of MC68040VRC : entity is
-- num cell port func safe [ccell dis rslt]
"0 (BC_2, RSTO, output2, X)," &
"1 (BC_2, IPEND, output2, X)," &
"2 (BC_2, CIOUT, output3, X, 161, 0, Z)," &
"3 (BC_2, UPA(0), output3, X, 161, 0, Z)," &
"4 (BC_2, UPA(1), output3, X, 161, 0, Z)," &
"5 (BC_2, TT(0), output3, X, 161, 0, Z)," &
"6 (BC_4, TT(0), input, X)," &
"7 (BC_2, TT(1), output3, X, 161, 0, Z)," &
"8 (BC_4, TT(1), input, X)," &
"9 (BC_2, A(10), output3, X, 153, 0, Z)," &
"10 (BC_4, A(10), input, X)," &
"11 (BC_2, A(11), output3, X, 153, 0, Z)," &
"12 (BC_4, A(11), input, X)," &
"13 (BC_2, A(12), output3, X, 153, 0, Z)," &
"14 (BC_4, A(12), input, X)," &
"15 (BC_2, A(13), output3, X, 153, 0, Z)," &
"16 (BC_4, A(13), input, X)," &
"17 (BC_2, A(14), output3, X, 153, 0, Z)," &
"18 (BC_4, A(14), input, X)," &
"19 (BC_2, A(15), output3, X, 153, 0, Z)," &
-- num cell port func safe [ccell dis rslt]
"20 (BC_4, A(15), input, X)," &
"21 (BC_2, A(16), output3, X, 153, 0, Z)," &
"22 (BC_4, A(16), input, X)," &
"23 (BC_2, A(17), output3, X, 153, 0, Z)," &
"24 (BC_4, A(17), input, X)," &
"25 (BC_2, A(18), output3, X, 153, 0, Z)," &
"26 (BC_4, A(18), input, X)," &
"27 (BC_2, A(19), output3, X, 153, 0, Z)," &
"28 (BC_4, A(19), input, X)," &
"29 (BC_2, A(20), output3, X, 153, 0, Z)," &
"30 (BC_4, A(20), input, X)," &
"31 (BC_2, A(21), output3, X, 153, 0, Z)," &
"32 (BC_4, A(21), input, X)," &
"33 (BC_2, A(22), output3, X, 153, 0, Z)," &
"34 (BC_4, A(22), input, X)," &
"35 (BC_2, A(23), output3, X, 153, 0, Z)," &
"36 (BC_4, A(23), input, X)," &
"37 (BC_2, A(24), output3, X, 153, 0, Z)," &
"38 (BC_4, A(24), input, X)," &
"39 (BC_2, A(25), output3, X, 153, 0, Z)," &
-- num cell port func safe [ccell dis rslt]
"40 (BC_4, A(25), input, X)," &
"41 (BC_2, A(26), output3, X, 153, 0, Z)," &
"42 (BC_4, A(26), input, X)," &
"43 (BC_2, A(27), output3, X, 153, 0, Z)," &
"44 (BC_4, A(27), input, X)," &
"45 (BC_2, A(28), output3, X, 153, 0, Z)," &
"46 (BC_4, A(28), input, X)," &
"47 (BC_2, A(29), output3, X, 153, 0, Z)," &
"48 (BC_4, A(29), input, X)," &
"49 (BC_2, A(30), output3, X, 153, 0, Z)," &
"50 (BC_4, A(30), input, X)," &
"51 (BC_2, A(31), output3, X, 153, 0, Z)," &
"52 (BC_4, A(31), input, X)," &
"53 (BC_2, D(0), output3, X, 154, 0, Z)," &
"54 (BC_2, D(1), output3, X, 154, 0, Z)," &
"55 (BC_2, D(2), output3, X, 154, 0, Z)," &
"56 (BC_2, D(3), output3, X, 154, 0, Z)," &
"57 (BC_2, D(4), output3, X, 154, 0, Z)," &
"58 (BC_2, D(5), output3, X, 154, 0, Z)," &
"59 (BC_2, D(6), output3, X, 154, 0, Z)," &
-- num cell port func safe [ccell dis rslt]
"60 (BC_2, D(7), output3, X, 154, 0, Z)," &
"61 (BC_2, D(8), output3, X, 154, 0, Z)," &
"62 (BC_2, D(9), output3, X, 154, 0, Z)," &
"63 (BC_2, D(10), output3, X, 154, 0, Z)," &
"64 (BC_2, D(11), output3, X, 154, 0, Z)," &
"65 (BC_2, D(12), output3, X, 154, 0, Z)," &
"66 (BC_2, D(13), output3, X, 154, 0, Z)," &
"67 (BC_2, D(14), output3, X, 154, 0, Z)," &
"68 (BC_2, D(15), output3, X, 154, 0, Z)," &
"69 (BC_2, D(16), output3, X, 154, 0, Z)," &
"70 (BC_2, D(17), output3, X, 154, 0, Z)," &
"71 (BC_2, D(18), output3, X, 154, 0, Z)," &
"72 (BC_2, D(19), output3, X, 154, 0, Z)," &
"73 (BC_2, D(20), output3, X, 154, 0, Z)," &
"74 (BC_2, D(21), output3, X, 154, 0, Z)," &
"75 (BC_2, D(22), output3, X, 154, 0, Z)," &
"76 (BC_2, D(23), output3, X, 154, 0, Z)," &
"77 (BC_2, D(24), output3, X, 154, 0, Z)," &
"78 (BC_2, D(25), output3, X, 154, 0, Z)," &
"79 (BC_2, D(26), output3, X, 154, 0, Z)," &
-- num cell port func safe [ccell dis rslt]
"80 (BC_2, D(27), output3, X, 154, 0, Z)," &
"81 (BC_2, D(28), output3, X, 154, 0, Z)," &
"82 (BC_2, D(29), output3, X, 154, 0, Z)," &
"83 (BC_2, D(30), output3, X, 154, 0, Z)," &
"84 (BC_2, D(31), output3, X, 154, 0, Z)," &
"85 (BC_4, *, internal, X)," &
"86 (BC_4, D(0), input, X)," &
"87 (BC_4, D(1), input, X)," &
"88 (BC_4, D(2), input, X)," &
"89 (BC_4, D(3), input, X)," &
"90 (BC_4, D(4), input, X)," &
"91 (BC_4, D(5), input, X)," &
"92 (BC_4, D(6), input, X)," &
"93 (BC_4, D(7), input, X)," &
"94 (BC_4, D(8), input, X)," &
"95 (BC_4, D(9), input, X)," &
"96 (BC_4, D(10), input, X)," &
"97 (BC_4, D(11), input, X)," &
"98 (BC_4, D(12), input, X)," &
"99 (BC_4, D(13), input, X)," &
-- num cell port func safe [ccell dis rslt]
"100 (BC_4, D(14), input, X)," &
"101 (BC_4, D(15), input, X)," &
"102 (BC_4, D(16), input, X)," &
"103 (BC_4, D(17), input, X)," &
"104 (BC_4, D(18), input, X)," &
"105 (BC_4, D(19), input, X)," &
"106 (BC_4, D(20), input, X)," &
"107 (BC_4, D(21), input, X)," &
"108 (BC_4, D(22), input, X)," &
"109 (BC_4, D(23), input, X)," &
"110 (BC_4, D(24), input, X)," &
"111 (BC_4, D(25), input, X)," &
"112 (BC_4, D(26), input, X)," &
"113 (BC_4, D(27), input, X)," &
"114 (BC_4, D(28), input, X)," &
"115 (BC_4, D(29), input, X)," &
"116 (BC_4, D(30), input, X)," &
"117 (BC_4, D(31), input, X)," &
"118 (BC_2, A(9), output3, X, 153, 0, Z)," &
"119 (BC_4, A(9), input, X)," &
-- num cell port func safe [ccell dis rslt]
"120 (BC_2, A(8), output3, X, 153, 0, Z)," &
"121 (BC_4, A(8), input, X)," &
"122 (BC_2, A(7), output3, X, 153, 0, Z)," &
"123 (BC_4, A(7), input, X)," &
"124 (BC_2, A(6), output3, X, 153, 0, Z)," &
"125 (BC_4, A(6), input, X)," &
"126 (BC_2, A(5), output3, X, 153, 0, Z)," &
"127 (BC_4, A(5), input, X)," &
"128 (BC_2, A(4), output3, X, 153, 0, Z)," &
"129 (BC_4, A(4), input, X)," &
"130 (BC_2, A(3), output3, X, 153, 0, Z)," &
"131 (BC_4, A(3), input, X)," &
"132 (BC_2, A(2), output3, X, 153, 0, Z)," &
"133 (BC_4, A(2), input, X)," &
"134 (BC_2, A(1), output3, X, 153, 0, Z)," &
"135 (BC_4, A(1), input, X)," &
"136 (BC_2, A(0), output3, X, 153, 0, Z)," &
"137 (BC_4, A(0), input, X)," &
"138 (BC_2, TM(2), output3, X, 161, 0, Z)," &
"139 (BC_2, TM(1), output3, X, 161, 0, Z)," &
-- num cell port func safe [ccell dis rslt]
"140 (BC_2, TM(0), output3, X, 161, 0, Z)," &
"141 (BC_2, TLN(1), output3, X, 161, 0, Z)," &
"142 (BC_2, TLN(0), output3, X, 161, 0, Z)," &
"143 (BC_2, SIZ(0), output3, X, 161, 0, Z)," &
"144 (BC_4, SIZ(0), input, X)," &
"145 (BC_2, R_W, output3, X, 161, 0, Z)," &
"146 (BC_4, R_W, input, X)," &
"147 (BC_2, LOCKE, output3, X, 160, 0, Z)," &
"148 (BC_2, SIZ(1), output3, X, 161, 0, Z)," &
"149 (BC_4, SIZ(1), input, X)," &
"150 (BC_2, LOCK, output3, X, 160, 0, Z)," &
"151 (BC_2, MI, output2, X)," &
"152 (BC_2, BR, output2, X)," &
"153 (BC_2, *, controlr, 0)," &
"154 (BC_2, *, controlr, 0)," &
"155 (BC_2, TS, output3, X, 161, 0, Z)," &
"156 (BC_4, TS, input, X)," &
"157 (BC_2, BB, output3, X, 160, 0, Z)," &
"158 (BC_4, BB, input, X)," &
"159 (BC_2, *, controlr, 0)," &
-- num cell port func safe [ccell dis rslt]
"160 (BC_2, *, controlr, 0)," &
"161 (BC_2, *, controlr, 0)," &
"162 (BC_2, TIP, output3, X, 160, 0, Z)," &
"163 (BC_2, PST(3), output2, X)," &
"164 (BC_2, PST(2), output2, X)," &
"165 (BC_2, PST(1), output2, X)," &
"166 (BC_2, PST(0), output2, X)," &
"167 (BC_2, TA, output3, X, 159, 0, Z)," &
"168 (BC_4, TA, input, X)," &
"169 (BC_4, TEA, input, X)," &
"170 (BC_4, BG, input, X)," &
"171 (BC_4, SC(1), input, X)," &
"172 (BC_4, SC(0), input, X)," &
"173 (BC_4, TBI, input, X)," &
"174 (BC_4, AVEC, input, X)," &
"175 (BC_4, TCI, input, X)," &
"176 (BC_4, TYLO2, input, X)," &
"177 (BC_2, SCD, output2, X)," &
"178 (BC_4, TYLO3, input, X)," &
"179 (BC_4, LFO, input, X)," &
-- num cell port func safe [ccell dis rslt]
"180 (BC_4, BCLK, input, X)," &
"181 (BC_4, IPL(0), input, X)," &
"182 (BC_4, IPL(1), input, X)," &
"183 (BC_4, IPL(2), input, X)," &
"184 (BC_4, RSTI, input, X)," &
"185 (BC_4, CDIS, input, X)," &
"186 (BC_4, MDIS, input, X)," &
"187 (BC_2, *, controlr, 0)," &
"188 (BC_2, LOC, output3, X, 187, 0, Z)," &
"189 (BC_4, LOC, input, X)";
end MC68040VRC;