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-- ======================================================================
-- Copyright 2013, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
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-- treaty provisions. Therefore, you must treat this software like any
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-- circuit described herein. Cypress' products described herein are not
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--
-- This software is protected by and subject to worldwide patent
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-- ======================================================================
-- $File: $
-- $Author: $
-- $Date: $
-- $Revision: $
-- ======================================================================
-- DO NOT EDIT THIS FILE. PLEASE CONTACT BSDL OWNER FOR UPDATES TO
-- ORIGINATING SCRIPT.
-- This file was automatically generated using ../scr/create_BSDL.pl.
-- Definitions File: ../run/PSoC5_Panther_pinouts_23.csv
-- timestamp: 2013-06-05 17:54:34
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8
--*****************************************************************************
entity CY8C58LPXXX is
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.2 -generic mapping parameter
--*****************************************************************************
generic (PHYSICAL_PIN_MAP : string := "TQFP100");
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.3 - logical port description
--*****************************************************************************
port (
P0_0 : inout bit; -- IO
P0_1 : inout bit; -- IO
P0_2 : inout bit; -- IO
P0_3 : inout bit; -- IO
P0_4 : inout bit; -- IO
P0_5 : inout bit; -- IO
P0_6 : inout bit; -- IO
P0_7 : inout bit; -- IO
P12_0 : inout bit; -- IO
P12_1 : inout bit; -- IO
P12_2 : inout bit; -- IO
P12_3 : inout bit; -- IO
P12_4 : inout bit; -- IO
P12_5 : inout bit; -- IO
P12_6 : inout bit; -- IO
P12_7 : inout bit; -- IO
P15_0 : inout bit; -- IO
P15_1 : inout bit; -- IO
P15_2 : inout bit; -- IO
P15_3 : inout bit; -- IO
P15_4 : inout bit; -- IO
P15_5 : inout bit; -- IO
P1_0 : in bit; -- I (TMS)
P1_1 : in bit; -- I (TCK)
P1_2 : inout bit; -- IO
P1_3 : out bit; -- O (TDO)
P1_4 : in bit; -- I (TDI)
P1_5 : in bit; -- I (NTRST)
P1_6 : inout bit; -- IO
P1_7 : inout bit; -- IO
P2_0 : inout bit; -- IO
P2_1 : inout bit; -- IO
P2_2 : inout bit; -- IO
P2_3 : inout bit; -- IO
P2_4 : inout bit; -- IO
P2_5 : inout bit; -- IO
P2_6 : inout bit; -- IO
P2_7 : inout bit; -- IO
P3_0 : inout bit; -- IO
P3_1 : inout bit; -- IO
P3_2 : inout bit; -- IO
P3_3 : inout bit; -- IO
P3_4 : inout bit; -- IO
P3_5 : inout bit; -- IO
P3_6 : inout bit; -- IO
P3_7 : inout bit; -- IO
P4_0 : inout bit; -- IO
P4_1 : inout bit; -- IO
P4_2 : inout bit; -- IO
P4_3 : inout bit; -- IO
P4_4 : inout bit; -- IO
P4_5 : inout bit; -- IO
P4_6 : inout bit; -- IO
P4_7 : inout bit; -- IO
P5_0 : inout bit; -- IO
P5_1 : inout bit; -- IO
P5_2 : inout bit; -- IO
P5_3 : inout bit; -- IO
P5_4 : inout bit; -- IO
P5_5 : inout bit; -- IO
P5_6 : inout bit; -- IO
P5_7 : inout bit; -- IO
P6_0 : inout bit; -- IO
P6_1 : inout bit; -- IO
P6_2 : inout bit; -- IO
P6_3 : inout bit; -- IO
P6_4 : inout bit; -- IO
P6_5 : inout bit; -- IO
P6_6 : inout bit; -- IO
P6_7 : inout bit; -- IO
XRES_N : in bit; -- I
IND : linkage bit; -- linkage
VB : linkage bit; -- linkage
VBAT : linkage bit; -- linkage
VCCA : linkage bit; -- linkage
VCCD : linkage bit_vector(0 to 1); -- linkage
VDDA : linkage bit; -- linkage
VDDD : linkage bit; -- linkage
VIO0 : linkage bit; -- linkage
VIO1 : linkage bit; -- linkage
VIO2 : linkage bit; -- linkage
VIO3 : linkage bit; -- linkage
VSSA : linkage bit; -- linkage
VSSB : linkage bit; -- linkage
VSSD : linkage bit_vector(0 to 1); -- linkage
VSSD : linkage bit_vector(0 to 1); -- linkage
VDDD : linkage bit -- linkage
);
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.4 - standard use statement
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.5 - use statement
--*****************************************************************************
use STD_1149_1_2001.all;
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.6 - component conformance statement
--*****************************************************************************
attribute COMPONENT_CONFORMANCE of CY8C58LPXXX : entity is "STD_1149_1_2001";
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.7 - device package pin mappings
--*****************************************************************************
attribute PIN_MAP of CY8C58LPXXX : entity is PHYSICAL_PIN_MAP;
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.8 - optional grouped port identification
--*****************************************************************************
constant TQFP100:PIN_MAP_STRING:=
" IND: 11, " &
" P0_0: 71, " &
" P0_1: 72, " &
" P0_2: 73, " &
" P0_3: 74, " &
" P0_4: 76, " &
" P0_5: 77, " &
" P0_6: 78, " &
" P0_7: 79, " &
" P12_0: 53, " &
" P12_1: 54, " &
" P12_2: 67, " &
" P12_3: 68, " &
" P12_4: 4, " &
" P12_5: 5, " &
" P12_6: 29, " &
" P12_7: 30, " &
" P15_0: 42, " &
" P15_1: 43, " &
" P15_2: 55, " &
" P15_3: 56, " &
" P15_4: 93, " &
" P15_5: 94, " &
" P1_0: 20, " &
" P1_1: 21, " &
" P1_2: 22, " &
" P1_3: 23, " &
" P1_4: 24, " &
" P1_5: 25, " &
" P1_6: 27, " &
" P1_7: 28, " &
" P2_0: 95, " &
" P2_1: 96, " &
" P2_2: 97, " &
" P2_3: 98, " &
" P2_4: 99, " &
" P2_5: 1, " &
" P2_6: 2, " &
" P2_7: 3, " &
" P3_0: 44, " &
" P3_1: 45, " &
" P3_2: 46, " &
" P3_3: 47, " &
" P3_4: 48, " &
" P3_5: 49, " &
" P3_6: 51, " &
" P3_7: 52, " &
" P4_0: 69, " &
" P4_1: 70, " &
" P4_2: 80, " &
" P4_3: 81, " &
" P4_4: 82, " &
" P4_5: 83, " &
" P4_6: 84, " &
" P4_7: 85, " &
" P5_0: 16, " &
" P5_1: 17, " &
" P5_2: 18, " &
" P5_3: 19, " &
" P5_4: 31, " &
" P5_5: 32, " &
" P5_6: 33, " &
" P5_7: 34, " &
" P6_0: 89, " &
" P6_1: 90, " &
" P6_2: 91, " &
" P6_3: 92, " &
" P6_4: 6, " &
" P6_5: 7, " &
" P6_6: 8, " &
" P6_7: 9, " &
" VB: 12, " &
" VBAT: 13, " &
" VCCA: 63, " &
" VCCD: (39,86), " &
" VDDA: 65, " &
" VDDD: 88, " &
" VIO0: 75, " &
" VIO1: 26, " &
" VIO2: 100, " &
" VIO3: 50, " &
" VSSA: 64, " &
" VSSB: 10, " &
" VSSD: (38,87), " &
" VSSD: (14,66), " &
" VDDD: 37, " &
" XRES_N: 15";
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.9 - scan port identification
--*****************************************************************************
attribute TAP_SCAN_IN of P1_4 : signal is true;
attribute TAP_SCAN_OUT of P1_3 : signal is true;
attribute TAP_SCAN_MODE of P1_0 : signal is true;
attribute TAP_SCAN_RESET of P1_5 : signal is true;
attribute TAP_SCAN_CLOCK of P1_1 : signal is (30.0e6, BOTH);
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.10 - optional compliance enable description
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.11 - instruction register description
--*****************************************************************************
attribute INSTRUCTION_LENGTH of CY8C58LPXXX : entity is 4;
-- From IROS Table 27-1.
attribute INSTRUCTION_OPCODE of CY8C58LPXXX : entity is
"EXTEST (0110)," &
"SAMPLE (0010)," & -- Sample/Preload
"PRELOAD (0010)," & -- Sample/Preload
"CLAMP (0101)," &
"INTEST (0100)," & -- Not to be published to customers
"DPACC (1010)," &
"APACC (1011)," &
"IDCODE (1110)," &
"SLEEP (1100)," &
"BYPASS (1111) ";
attribute INSTRUCTION_CAPTURE of CY8C58LPXXX: entity is "0001";
attribute INSTRUCTION_PRIVATE of CY8C58LPXXX: entity is
"DPACC, APACC, SLEEP";
-- From IROS Table 27-2.
attribute IDCODE_REGISTER of CY8C58LPXXX : entity is
"XXXX" & -- Reserved for version number
"11100001" & -- Hard-coded Part Number (0xE0)
"XXXXXXXX" & -- NV-Latch Part Number
"00000110100" & -- Manufacturer ID (0x069>>1) -> 0x034
"1"; -- ID register Presence indicator
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.12 - optional register description
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.13 - optional register access description
--*****************************************************************************
attribute REGISTER_ACCESS of CY8C58LPXXX : entity is
"BOUNDARY (EXTEST,PRELOAD,INTEST)," &
"BYPASS (BYPASS)";
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.14 - boundary-scan register description
--*****************************************************************************
attribute BOUNDARY_LENGTH of CY8C58LPXXX : entity is 137;
attribute BOUNDARY_REGISTER of CY8C58LPXXX : entity is
-- num (cell, port, function, safe, [ccell, disval, rslt])
-- P1_2 IO group
"0 (BC_2, *, control, 0), " &
"1 (BC_7, P1_2, bidir, 1, 0, 0, Z), " &
-- P5_3 IO group
"2 (BC_2, *, control, 0), " &
"3 (BC_7, P5_3, bidir, X, 2, 0, Z), " &
-- P5_2 IO group
"4 (BC_2, *, control, 0), " &
"5 (BC_7, P5_2, bidir, X, 4, 0, Z), " &
-- P5_1 IO group
"6 (BC_2, *, control, 0), " &
"7 (BC_7, P5_1, bidir, X, 6, 0, Z), " &
-- P5_0 IO group
"8 (BC_2, *, control, 0), " &
"9 (BC_7, P5_0, bidir, X, 8, 0, Z), " &
-- XRES_N I group
"10 (BC_2, XRES_N, input, 1), " &
-- P6_7 IO group
"11 (BC_2, *, control, 0), " &
"12 (BC_7, P6_7, bidir, X, 11, 0, Z), " &
-- P6_6 IO group
"13 (BC_2, *, control, 0), " &
"14 (BC_7, P6_6, bidir, X, 13, 0, Z), " &
-- P6_5 IO group
"15 (BC_2, *, control, 0), " &
"16 (BC_7, P6_5, bidir, X, 15, 0, Z), " &
-- P6_4 IO group
"17 (BC_2, *, control, 0), " &
"18 (BC_7, P6_4, bidir, X, 17, 0, Z), " &
-- P12_5 IO group
"19 (BC_2, *, control, 0), " &
"20 (BC_7, P12_5, bidir, X, 19, 0, Z), " &
-- P12_4 IO group
"21 (BC_2, *, control, 0), " &
"22 (BC_7, P12_4, bidir, X, 21, 0, Z), " &
-- P2_7 IO group
"23 (BC_2, *, control, 0), " &
"24 (BC_7, P2_7, bidir, X, 23, 0, Z), " &
-- P2_6 IO group
"25 (BC_2, *, control, 0), " &
"26 (BC_7, P2_6, bidir, X, 25, 0, Z), " &
-- P2_5 IO group
"27 (BC_2, *, control, 0), " &
"28 (BC_7, P2_5, bidir, X, 27, 0, Z), " &
-- P2_4 IO group
"29 (BC_2, *, control, 0), " &
"30 (BC_7, P2_4, bidir, X, 29, 0, Z), " &
-- P2_3 IO group
"31 (BC_2, *, control, 0), " &
"32 (BC_7, P2_3, bidir, X, 31, 0, Z), " &
-- P2_2 IO group
"33 (BC_2, *, control, 0), " &
"34 (BC_7, P2_2, bidir, X, 33, 0, Z), " &
-- P2_1 IO group
"35 (BC_2, *, control, 0), " &
"36 (BC_7, P2_1, bidir, X, 35, 0, Z), " &
-- P2_0 IO group
"37 (BC_2, *, control, 0), " &
"38 (BC_7, P2_0, bidir, X, 37, 0, Z), " &
-- P15_5 IO group
"39 (BC_2, *, control, 0), " &
"40 (BC_7, P15_5, bidir, X, 39, 0, Z), " &
-- P15_4 IO group
"41 (BC_2, *, control, 0), " &
"42 (BC_7, P15_4, bidir, X, 41, 0, Z), " &
-- P6_3 IO group
"43 (BC_2, *, control, 0), " &
"44 (BC_7, P6_3, bidir, X, 43, 0, Z), " &
-- P6_2 IO group
"45 (BC_2, *, control, 0), " &
"46 (BC_7, P6_2, bidir, X, 45, 0, Z), " &
-- P6_1 IO group
"47 (BC_2, *, control, 0), " &
"48 (BC_7, P6_1, bidir, X, 47, 0, Z), " &
-- P6_0 IO group
"49 (BC_2, *, control, 0), " &
"50 (BC_7, P6_0, bidir, X, 49, 0, Z), " &
-- P4_7 IO group
"51 (BC_2, *, control, 0), " &
"52 (BC_7, P4_7, bidir, X, 51, 0, Z), " &
-- P4_6 IO group
"53 (BC_2, *, control, 0), " &
"54 (BC_7, P4_6, bidir, X, 53, 0, Z), " &
-- P4_5 IO group
"55 (BC_2, *, control, 0), " &
"56 (BC_7, P4_5, bidir, X, 55, 0, Z), " &
-- P4_4 IO group
"57 (BC_2, *, control, 0), " &
"58 (BC_7, P4_4, bidir, X, 57, 0, Z), " &
-- P4_3 IO group
"59 (BC_2, *, control, 0), " &
"60 (BC_7, P4_3, bidir, X, 59, 0, Z), " &
-- P4_2 IO group
"61 (BC_2, *, control, 0), " &
"62 (BC_7, P4_2, bidir, X, 61, 0, Z), " &
-- P0_7 IO group
"63 (BC_2, *, control, 0), " &
"64 (BC_7, P0_7, bidir, X, 63, 0, Z), " &
-- P0_6 IO group
"65 (BC_2, *, control, 0), " &
"66 (BC_7, P0_6, bidir, X, 65, 0, Z), " &
-- P0_5 IO group
"67 (BC_2, *, control, 0), " &
"68 (BC_7, P0_5, bidir, X, 67, 0, Z), " &
-- P0_4 IO group
"69 (BC_2, *, control, 0), " &
"70 (BC_7, P0_4, bidir, X, 69, 0, Z), " &
-- P0_3 IO group
"71 (BC_2, *, control, 0), " &
"72 (BC_7, P0_3, bidir, X, 71, 0, Z), " &
-- P0_2 IO group
"73 (BC_2, *, control, 0), " &
"74 (BC_7, P0_2, bidir, X, 73, 0, Z), " &
-- P0_1 IO group
"75 (BC_2, *, control, 0), " &
"76 (BC_7, P0_1, bidir, X, 75, 0, Z), " &
-- P0_0 IO group
"77 (BC_2, *, control, 0), " &
"78 (BC_7, P0_0, bidir, X, 77, 0, Z), " &
-- P4_1 IO group
"79 (BC_2, *, control, 0), " &
"80 (BC_7, P4_1, bidir, X, 79, 0, Z), " &
-- P4_0 IO group
"81 (BC_2, *, control, 0), " &
"82 (BC_7, P4_0, bidir, X, 81, 0, Z), " &
-- P12_3 IO group
"83 (BC_2, *, control, 0), " &
"84 (BC_7, P12_3, bidir, X, 83, 0, Z), " &
-- P12_2 IO group
"85 (BC_2, *, control, 0), " &
"86 (BC_7, P12_2, bidir, X, 85, 0, Z), " &
-- P15_3 IO group
"87 (BC_2, *, control, 0), " &
"88 (BC_7, P15_3, bidir, X, 87, 0, Z), " &
-- P15_2 IO group
"89 (BC_2, *, control, 0), " &
"90 (BC_7, P15_2, bidir, X, 89, 0, Z), " &
-- P12_1 IO group
"91 (BC_2, *, control, 0), " &
"92 (BC_7, P12_1, bidir, X, 91, 0, Z), " &
-- P12_0 IO group
"93 (BC_2, *, control, 0), " &
"94 (BC_7, P12_0, bidir, X, 93, 0, Z), " &
-- P3_7 IO group
"95 (BC_2, *, control, 0), " &
"96 (BC_7, P3_7, bidir, X, 95, 0, Z), " &
-- P3_6 IO group
"97 (BC_2, *, control, 0), " &
"98 (BC_7, P3_6, bidir, X, 97, 0, Z), " &
-- P3_5 IO group
"99 (BC_2, *, control, 0), " &
"100 (BC_7, P3_5, bidir, X, 99, 0, Z), " &
-- P3_4 IO group
"101 (BC_2, *, control, 0), " &
"102 (BC_7, P3_4, bidir, X, 101, 0, Z), " &
-- P3_3 IO group
"103 (BC_2, *, control, 0), " &
"104 (BC_7, P3_3, bidir, X, 103, 0, Z), " &
-- P3_2 IO group
"105 (BC_2, *, control, 0), " &
"106 (BC_7, P3_2, bidir, X, 105, 0, Z), " &
-- P3_1 IO group
"107 (BC_2, *, control, 0), " &
"108 (BC_7, P3_1, bidir, X, 107, 0, Z), " &
-- P3_0 IO group
"109 (BC_2, *, control, 0), " &
"110 (BC_7, P3_0, bidir, X, 109, 0, Z), " &
-- P15_1 IO group
"111 (BC_2, *, control, 0), " &
"112 (BC_7, P15_1, bidir, X, 111, 0, Z), " &
-- P15_0 IO group
"113 (BC_2, *, control, 0), " &
"114 (BC_7, P15_0, bidir, X, 113, 0, Z), " &
-- internal group
"115 (BC_0, *, internal, X), " &
"116 (BC_0, *, internal, X), " &
"117 (BC_0, *, internal, X), " &
"118 (BC_0, *, internal, X), " &
"119 (BC_0, *, internal, X), " &
"120 (BC_0, *, internal, X), " &
-- P5_7 IO group
"121 (BC_2, *, control, 0), " &
"122 (BC_7, P5_7, bidir, X, 121, 0, Z), " &
-- P5_6 IO group
"123 (BC_2, *, control, 0), " &
"124 (BC_7, P5_6, bidir, X, 123, 0, Z), " &
-- P5_5 IO group
"125 (BC_2, *, control, 0), " &
"126 (BC_7, P5_5, bidir, X, 125, 0, Z), " &
-- P5_4 IO group
"127 (BC_2, *, control, 0), " &
"128 (BC_7, P5_4, bidir, X, 127, 0, Z), " &
-- P12_7 IO group
"129 (BC_2, *, control, 0), " &
"130 (BC_7, P12_7, bidir, X, 129, 0, Z), " &
-- P12_6 IO group
"131 (BC_2, *, control, 0), " &
"132 (BC_7, P12_6, bidir, X, 131, 0, Z), " &
-- P1_7 IO group
"133 (BC_2, *, control, 0), " &
"134 (BC_7, P1_7, bidir, X, 133, 0, Z), " &
-- P1_6 IO group
"135 (BC_2, *, control, 0), " &
"136 (BC_7, P1_6, bidir, X, 135, 0, Z)";
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.15 - optional runbist description
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.16 - optional intest description
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.17 - optional BSDL extensions
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.18 - optional design warning
--*****************************************************************************
attribute DESIGN_WARNING of CY8C58LPXXX : entity is
"This CY8C58LPXXX TQFP100 BSDL file supports 1149.1 testing only after "&
"two of the following conditions are satisfied: "&
"1. The JTAG port is enabled. "&
"2. All IOs are pre-configured to drive out fast strong high/low. "&
"JTAG access can be enabled either through programming NV-Latch "&
"bits appropriately or through using test-port acquisition protocol. "&
"The IOs may be pre-configuration either by writing port "&
"configuration registers directly through a test port, or relying "&
"on a programmed boot sequence which does that to complete automatically. "&
"Testing other IO configurations requires changes to this file and "&
"the pre-configured IO configuration.";
-- You can put any other special care instructions here if needed.
end CY8C58LPXXX;