--
-- BSDL File created/edited by BCAD BSD Editor Version 3.1
--
--BSDE:Revision: 1.0
--BSDE:Description: RS8250 (PEAK7) in 156 BGA
entity RS8250 is
generic (PHYSICAL_PIN_MAP : string := "BGA156" );
port (
CLK8KHZIN: in bit;
GND: linkage bit;
MADDR: in bit_vector (0 to 6);
MAS_MWR: in bit;
MCLK_MACSSEL: in bit;
MCS: in bit;
MDATA: inout bit_vector (0 to 7);
MINT: out bit;
MSYNCMODE: in bit;
MWR_MRD: in bit;
NC: linkage bit;
ONESECIN: in bit;
ONESECOUT: out bit;
PWR: linkage bit;
RESET: in bit;
RXFRAMEREF: out bit;
STATOUT: out bit_vector (0 to 7);
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
TRST: in bit;
TXDL: in bit;
TXFRAMEREF: out bit;
URXADDR: in bit_vector (0 to 4);
URXCLAV: out bit;
URXCLK: in bit;
URXDATA: out bit_vector (0 to 15);
URXENB: in bit;
URXPRTY: out bit;
URXSOC: out bit;
UTXADDR: in bit_vector (0 to 4);
UTXCLAV: out bit;
UTXCLK: in bit;
UTXDATA: in bit_vector (0 to 15);
UTXENB: in bit;
UTXPRTY: in bit;
UTXSOC: in bit;
VGG: linkage bit
);
use STD_1149_1_1994.all;
use BCAD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of RS8250 :
entity is "STD_1149_1_1993";
attribute PIN_MAP of RS8250 : entity is PHYSICAL_PIN_MAP;
constant BGA156: PIN_MAP_STRING:=
"CLK8KHZIN:N3," &
"GND:L1," &
"MADDR:(G2,F4,F3,F1,F2,E4,E3)," &
"MAS_MWR:D2," &
"MCLK_MACSSEL:L3," &
"MCS:C1," &
"MDATA:(K2,K3,K1,J4,J1,H2,H1,G3)," &
"MINT:B1," &
"MSYNCMODE:M1," &
"MWR_MRD:C2," &
"NC:P14," &
"ONESECIN:M2," &
"ONESECOUT:N1," &
"PWR:M7," &
"RESET:M3," &
"RXFRAMEREF:P2," &
"STATOUT:(B2,A2,B3,C3,A3,B4,C4,A4)," &
"TCK:N4," &
"TDI:L4," &
"TDO:N5," &
"TMS:P4," &
"TRST:M4," &
"TXDL:P3," &
"TXFRAMEREF:N2," &
"URXADDR:(D6,A5,C5,B5,D5)," &
"URXCLAV:C12," &
"URXCLK:C14," &
"URXDATA:(B12,A12,B11,A11,D11,B10,A10,B9,A9,C9," &
"D9,B8,C8,A7,B7,A6)," &
"URXENB:C13," &
"URXPRTY:C6," &
"URXSOC:B14," &
"UTXADDR:(P12,M12,N12,P13,N13)," &
"UTXCLAV:E12," &
"UTXCLK:D14," &
"UTXDATA:(M14,L13,L14,K13,K14,J14,J12,J11,H13,H14," &
"H11,G12,G14,G13,F14,F13)," &
"UTXENB:E11," &
"UTXPRTY:E14," &
"UTXSOC:E13," &
"VGG:N11";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (2.00e+07, BOTH);
attribute TAP_SCAN_RESET of TRST : signal is true;
attribute INSTRUCTION_LENGTH of RS8250 : entity is 3;
attribute INSTRUCTION_OPCODE of RS8250 : entity is
"BYPASS ( 111)," &
"EXTEST ( 000)," &
"INTEST ( 010)," &
"PRIVATE1 ( 011)," &
"RESERVED1 ( 100)," &
"RESERVED2 ( 101)," &
"RESERVED3 ( 110)," &
"SAMPLE ( 001)" ;
attribute INSTRUCTION_CAPTURE of RS8250 : entity is "001";
attribute INSTRUCTION_PRIVATE of RS8250 : entity is
" PRIVATE1, RESERVED1, RESERVED2, RESERVED3";
attribute REGISTER_ACCESS of RS8250 : entity is
"BYPASS ( BYPASS, PRIVATE1, RESERVED1, RESERVED2, RESERVED3)," &
"BOUNDARY ( EXTEST, INTEST, SAMPLE)";
attribute BOUNDARY_LENGTH of RS8250 : entity is 104;
attribute BOUNDARY_REGISTER of RS8250 : entity is
" 0 (BC_1, TXDL, input, 0)," &
" 1 (BC_1, CLK8KHZIN, input, 0)," &
" 2 (BC_1, *, controlr, 1)," &
" 3 (BC_1, RXFRAMEREF, output3, X, 2, 1, Z)," &
" 4 (BC_1, *, controlr, 1)," &
" 5 (BC_1, TXFRAMEREF, output3, X, 4, 1, Z)," &
" 6 (BC_1, *, controlr, 1)," &
" 7 (BC_1, ONESECOUT, output3, X, 6, 1, Z)," &
" 8 (BC_1, ONESECIN, input, 0)," &
" 9 (BC_1, RESET, input, 0)," &
" 10 (BC_1, MSYNCMODE, input, 1)," &
" 11 (BC_1, MCLK_MACSSEL, input, 0)," &
" 12 (BC_1, *, controlr, 1)," &
" 13 (BC_7, MDATA(0), bidir, X, 12, 1, Z)," &
" 14 (BC_7, MDATA(1), bidir, X, 12, 1, Z)," &
" 15 (BC_1, *, controlr, 1)," &
" 16 (BC_7, MDATA(2), bidir, X, 15, 1, Z)," &
" 17 (BC_7, MDATA(3), bidir, X, 15, 1, Z)," &
" 18 (BC_7, MDATA(4), bidir, X, 12, 1, Z)," &
" 19 (BC_7, MDATA(5), bidir, X, 12, 1, Z)," &
" 20 (BC_7, MDATA(6), bidir, X, 15, 1, Z)," &
" 21 (BC_7, MDATA(7), bidir, X, 15, 1, Z)," &
" 22 (BC_1, *, internal, 1)," &
" 23 (BC_1, *, internal, 1)," &
" 24 (BC_1, MADDR(0), input, 0)," &
" 25 (BC_1, MADDR(1), input, 0)," &
" 26 (BC_1, MADDR(2), input, 0)," &
" 27 (BC_1, MADDR(3), input, 0)," &
" 28 (BC_1, MADDR(4), input, 0)," &
" 29 (BC_1, MADDR(5), input, 0)," &
" 30 (BC_1, MADDR(6), input, 0)," &
" 31 (BC_1, *, internal, 0)," &
" 32 (BC_1, *, internal, 0)," &
" 33 (BC_1, MAS_MWR, input, 1)," &
" 34 (BC_1, MCS, input, 1)," &
" 35 (BC_1, MWR_MRD, input, 1)," &
" 36 (BC_1, *, controlr, 1)," &
" 37 (BC_1, MINT, output3, X, 36, 1, Z)," &
" 38 (BC_1, *, controlr, 1)," &
" 39 (BC_1, STATOUT(0), output3, X, 38, 1, Z)," &
" 40 (BC_1, STATOUT(1), output3, X, 38, 1, Z)," &
" 41 (BC_1, STATOUT(2), output3, X, 38, 1, Z)," &
" 42 (BC_1, STATOUT(3), output3, X, 38, 1, Z)," &
" 43 (BC_1, STATOUT(4), output3, X, 38, 1, Z)," &
" 44 (BC_1, STATOUT(5), output3, X, 38, 1, Z)," &
" 45 (BC_1, STATOUT(6), output3, X, 38, 1, Z)," &
" 46 (BC_1, STATOUT(7), output3, X, 38, 1, Z)," &
" 47 (BC_1, URXADDR(4), input, 1)," &
" 48 (BC_1, URXADDR(3), input, 1)," &
" 49 (BC_1, URXADDR(2), input, 1)," &
" 50 (BC_1, URXADDR(1), input, 1)," &
" 51 (BC_1, URXADDR(0), input, 1)," &
" 52 (BC_1, URXPRTY, output3, X, 68, 1, Z)," &
" 53 (BC_1, URXDATA(15), output3, X, 68, 1, Z)," &
" 54 (BC_1, URXDATA(14), output3, X, 70, 1, Z)," &
" 55 (BC_1, URXDATA(13), output3, X, 70, 1, Z)," &
" 56 (BC_1, URXDATA(12), output3, X, 70, 1, Z)," &
" 57 (BC_1, URXDATA(11), output3, X, 68, 1, Z)," &
" 58 (BC_1, URXDATA(10), output3, X, 68, 1, Z)," &
" 59 (BC_1, URXDATA(9), output3, X, 70, 1, Z)," &
" 60 (BC_1, URXDATA(8), output3, X, 70, 1, Z)," &
" 61 (BC_1, URXDATA(7), output3, X, 70, 1, Z)," &
" 62 (BC_1, URXDATA(6), output3, X, 68, 1, Z)," &
" 63 (BC_1, URXDATA(5), output3, X, 68, 1, Z)," &
" 64 (BC_1, URXDATA(4), output3, X, 70, 1, Z)," &
" 65 (BC_1, URXDATA(3), output3, X, 70, 1, Z)," &
" 66 (BC_1, URXDATA(2), output3, X, 70, 1, Z)," &
" 67 (BC_1, URXDATA(1), output3, X, 68, 1, Z)," &
" 68 (BC_1, *, controlr, 1)," &
" 69 (BC_1, URXDATA(0), output3, X, 68, 1, Z)," &
" 70 (BC_1, *, controlr, 1)," &
" 71 (BC_1, URXSOC, output3, 0, 70, 1, Z)," &
" 72 (BC_1, URXENB, input, 1)," &
" 73 (BC_1, *, controlr, 1)," &
" 74 (BC_1, URXCLAV, output3, 0, 73, 1, Z)," &
" 75 (BC_1, URXCLK, input, 0)," &
" 76 (BC_1, UTXCLK, input, 0)," &
" 77 (BC_1, UTXENB, input, 1)," &
" 78 (BC_1, UTXSOC, input, 0)," &
" 79 (BC_1, *, controlr, 1)," &
" 80 (BC_1, UTXCLAV, output3, 0, 79, 1, Z)," &
" 81 (BC_1, UTXPRTY, input, 0)," &
" 82 (BC_1, UTXDATA(15), input, 0)," &
" 83 (BC_1, UTXDATA(14), input, 0)," &
" 84 (BC_1, UTXDATA(13), input, 0)," &
" 85 (BC_1, UTXDATA(12), input, 0)," &
" 86 (BC_1, UTXDATA(11), input, 0)," &
" 87 (BC_1, UTXDATA(10), input, 0)," &
" 88 (BC_1, UTXDATA(9), input, 0)," &
" 89 (BC_1, UTXDATA(8), input, 0)," &
" 90 (BC_1, UTXDATA(7), input, 0)," &
" 91 (BC_1, UTXDATA(6), input, 0)," &
" 92 (BC_1, UTXDATA(5), input, 0)," &
" 93 (BC_1, UTXDATA(4), input, 0)," &
" 94 (BC_1, UTXDATA(3), input, 0)," &
" 95 (BC_1, UTXDATA(2), input, 0)," &
" 96 (BC_1, UTXDATA(1), input, 0)," &
" 97 (BC_1, UTXDATA(0), input, 0)," &
" 98 (BC_1, UTXADDR(4), input, 1)," &
" 99 (BC_1, UTXADDR(3), input, 1)," &
" 100 (BC_1, UTXADDR(2), input, 1)," &
" 101 (BC_1, UTXADDR(1), input, 1)," &
" 102 (BC_1, UTXADDR(0), input, 1)," &
" 103 (BC_1, *, internal, X)";
end RS8250;