-- ======================================================================
-- Copyright 2011, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or implied,
-- with regard to this material, including, but not limited to, the
-- implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- ======================================================================
-- $File: $
-- $Author: $
-- $Date: $
-- $Revision: $
-- ======================================================================
-- DO NOT EDIT THIS FILE. PLEASE CONTACT YIR FOR UPDATES TO ORIGINATING
-- SCRIPT.
-- This file was automatically generated using ../scr/create_BSDL.pl.
-- Definitions File: ../run/PSoC3_Pinouts_65.csv
-- timestamp: 2011-03-15 09:20:45
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8
--*****************************************************************************
entity CY8C3XXXX_XXX is
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.2 -generic mapping parameter
--*****************************************************************************
generic (PHYSICAL_PIN_MAP : string := "QFN48");
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.3 - logical port description
--*****************************************************************************
port (
P0_0 : inout bit; -- IO
P0_1 : inout bit; -- IO
P0_2 : inout bit; -- IO
P0_3 : inout bit; -- IO
P0_4 : inout bit; -- IO
P0_5 : inout bit; -- IO
P0_6 : inout bit; -- IO
P0_7 : inout bit; -- IO
P12_0 : inout bit; -- IO
P12_1 : inout bit; -- IO
P12_2 : inout bit; -- IO
P12_3 : inout bit; -- IO
P15_0 : inout bit; -- IO
P15_1 : inout bit; -- IO
P15_2 : inout bit; -- IO
P15_3 : inout bit; -- IO
P15_6 : buffer bit; -- O
P15_7 : buffer bit; -- O
P1_0 : in bit; -- I (TMS)
P1_1 : in bit; -- I (TCK)
P1_2 : inout bit; -- IO
P1_3 : out bit; -- O (TDO)
P1_4 : in bit; -- I (TDI)
P1_5 : inout bit; -- IO
P1_6 : inout bit; -- IO
P1_7 : inout bit; -- IO
P2_3 : inout bit; -- IO
P2_4 : inout bit; -- IO
P2_5 : inout bit; -- IO
P2_6 : inout bit; -- IO
P2_7 : inout bit; -- IO
IND : linkage bit; -- linkage
VB : linkage bit; -- linkage
VBAT : linkage bit; -- linkage
VCCA : linkage bit; -- linkage
VCCD : linkage bit_vector(0 to 1); -- linkage
VDDD : linkage bit; -- linkage
VDDOPAMP : linkage bit; -- linkage
VIO0 : linkage bit; -- linkage
VIO1 : linkage bit; -- linkage
VIO2 : linkage bit; -- linkage
VIO3 : linkage bit; -- linkage
VSSB : linkage bit; -- linkage
VSSD : linkage bit_vector(0 to 1); -- linkage
VSSOPAMP : linkage bit; -- linkage
VUSB : linkage bit -- linkage
);
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.4 - standard use statement
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.5 - use statement
--*****************************************************************************
use STD_1149_1_2001.all;
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.6 - component conformance statement
--*****************************************************************************
attribute COMPONENT_CONFORMANCE of CY8C3XXXX_XXX : entity is "STD_1149_1_2001";
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.7 - device package pin mappings
--*****************************************************************************
attribute PIN_MAP of CY8C3XXXX_XXX : entity is PHYSICAL_PIN_MAP;
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.8 - optional grouped port identification
--*****************************************************************************
constant QFN48:PIN_MAP_STRING:=
" IND: 4, " &
" P0_0: 33, " &
" P0_1: 34, " &
" P0_2: 35, " &
" P0_3: 36, " &
" P0_4: 38, " &
" P0_5: 39, " &
" P0_6: 40, " &
" P0_7: 41, " &
" P12_0: 24, " &
" P12_1: 25, " &
" P12_2: 31, " &
" P12_3: 32, " &
" P15_0: 21, " &
" P15_1: 22, " &
" P15_2: 26, " &
" P15_3: 27, " &
" P15_6: 16, " &
" P15_7: 17, " &
" P1_0: 7, " &
" P1_1: 8, " &
" P1_2: 9, " &
" P1_3: 10, " &
" P1_4: 11, " &
" P1_5: 12, " &
" P1_6: 14, " &
" P1_7: 15, " &
" P2_3: 45, " &
" P2_4: 46, " &
" P2_5: 48, " &
" P2_6: 1, " &
" P2_7: 2, " &
" VB: 5, " &
" VBAT: 6, " &
" VCCA: 28, " &
" VCCD: (20,42), " &
" VDDD: 44, " &
" VDDOPAMP: 30, " &
" VIO0: 37, " &
" VIO1: 13, " &
" VIO2: 47, " &
" VIO3: 23, " &
" VSSB: 3, " &
" VSSD: (19,43), " &
" VSSOPAMP: 29, " &
" VUSB: 18";
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.9 - scan port identification
--*****************************************************************************
attribute TAP_SCAN_IN of P1_4 : signal is true;
attribute TAP_SCAN_OUT of P1_3 : signal is true;
attribute TAP_SCAN_MODE of P1_0 : signal is true;
attribute TAP_SCAN_CLOCK of P1_1 : signal is (30.0e6, BOTH);
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.10 - optional compliance enable description
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.11 - instruction register description
--*****************************************************************************
attribute INSTRUCTION_LENGTH of CY8C3XXXX_XXX : entity is 4;
-- From IROS Table 27-1.
attribute INSTRUCTION_OPCODE of CY8C3XXXX_XXX : entity is
"EXTEST (0000)," &
"SAMPLE (0010)," & -- Sample/Preload
"PRELOAD (0010)," & -- Sample/Preload
"CLAMP (0101)," &
"INTEST (0100)," & -- Not to be published to customers
"DPACC (1010)," &
"APACC (1011)," &
"IDCODE (1110)," &
"SLEEP (1100)," &
"BYPASS (1111) ";
attribute INSTRUCTION_CAPTURE of CY8C3XXXX_XXX: entity is "0001";
attribute INSTRUCTION_PRIVATE of CY8C3XXXX_XXX: entity is
"DPACC, APACC, SLEEP";
-- From IROS Table 27-2.
attribute IDCODE_REGISTER of CY8C3XXXX_XXX : entity is
"XXXX" & -- Reserved for version number
"11100000" & -- Hard-coded Part Number (0xE0)
"XXXXXXXX" & -- NV-Latch Part Number
"00000110100" & -- Manufacturer ID (0x069>>1) -> 0x034
"1"; -- ID register Presence indicator
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.12 - optional register description
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.13 - optional register access description
--*****************************************************************************
attribute REGISTER_ACCESS of CY8C3XXXX_XXX : entity is
"BOUNDARY (EXTEST,PRELOAD,INTEST)," &
"BYPASS (BYPASS)";
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.14 - boundary-scan register description
--*****************************************************************************
attribute BOUNDARY_LENGTH of CY8C3XXXX_XXX : entity is 139;
attribute BOUNDARY_REGISTER of CY8C3XXXX_XXX : entity is
-- num (cell, port, function, safe, [ccell, disval, rslt])
-- P1_2 IO group
"0 (BC_2, *, control, 0), " &
"1 (BC_7, P1_2, bidir, 1, 0, 0, Z), " &
-- internal group
"2 (BC_0, *, internal, X), " &
"3 (BC_0, *, internal, X), " &
-- internal group
"4 (BC_0, *, internal, X), " &
"5 (BC_0, *, internal, X), " &
-- internal group
"6 (BC_0, *, internal, X), " &
"7 (BC_0, *, internal, X), " &
-- internal group
"8 (BC_0, *, internal, X), " &
"9 (BC_0, *, internal, X), " &
-- internal group
"10 (BC_0, *, internal, X), " &
-- internal group
"11 (BC_0, *, internal, X), " &
"12 (BC_0, *, internal, X), " &
-- internal group
"13 (BC_0, *, internal, X), " &
"14 (BC_0, *, internal, X), " &
-- internal group
"15 (BC_0, *, internal, X), " &
"16 (BC_0, *, internal, X), " &
-- internal group
"17 (BC_0, *, internal, X), " &
"18 (BC_0, *, internal, X), " &
-- internal group
"19 (BC_0, *, internal, X), " &
"20 (BC_0, *, internal, X), " &
-- internal group
"21 (BC_0, *, internal, X), " &
"22 (BC_0, *, internal, X), " &
-- P2_7 IO group
"23 (BC_2, *, control, 0), " &
"24 (BC_7, P2_7, bidir, X, 23, 0, Z), " &
-- P2_6 IO group
"25 (BC_2, *, control, 0), " &
"26 (BC_7, P2_6, bidir, X, 25, 0, Z), " &
-- P2_5 IO group
"27 (BC_2, *, control, 0), " &
"28 (BC_7, P2_5, bidir, X, 27, 0, Z), " &
-- P2_4 IO group
"29 (BC_2, *, control, 0), " &
"30 (BC_7, P2_4, bidir, X, 29, 0, Z), " &
-- P2_3 IO group
"31 (BC_2, *, control, 0), " &
"32 (BC_7, P2_3, bidir, X, 31, 0, Z), " &
-- internal group
"33 (BC_0, *, internal, X), " &
"34 (BC_0, *, internal, X), " &
-- internal group
"35 (BC_0, *, internal, X), " &
"36 (BC_0, *, internal, X), " &
-- internal group
"37 (BC_0, *, internal, X), " &
"38 (BC_0, *, internal, X), " &
-- internal group
"39 (BC_0, *, internal, X), " &
"40 (BC_0, *, internal, X), " &
-- internal group
"41 (BC_0, *, internal, X), " &
"42 (BC_0, *, internal, X), " &
-- internal group
"43 (BC_0, *, internal, X), " &
"44 (BC_0, *, internal, X), " &
-- internal group
"45 (BC_0, *, internal, X), " &
"46 (BC_0, *, internal, X), " &
-- internal group
"47 (BC_0, *, internal, X), " &
"48 (BC_0, *, internal, X), " &
-- internal group
"49 (BC_0, *, internal, X), " &
"50 (BC_0, *, internal, X), " &
-- internal group
"51 (BC_0, *, internal, X), " &
"52 (BC_0, *, internal, X), " &
-- internal group
"53 (BC_0, *, internal, X), " &
"54 (BC_0, *, internal, X), " &
-- internal group
"55 (BC_0, *, internal, X), " &
"56 (BC_0, *, internal, X), " &
-- internal group
"57 (BC_0, *, internal, X), " &
"58 (BC_0, *, internal, X), " &
-- internal group
"59 (BC_0, *, internal, X), " &
"60 (BC_0, *, internal, X), " &
-- internal group
"61 (BC_0, *, internal, X), " &
"62 (BC_0, *, internal, X), " &
-- P0_7 IO group
"63 (BC_2, *, control, 0), " &
"64 (BC_7, P0_7, bidir, X, 63, 0, Z), " &
-- P0_6 IO group
"65 (BC_2, *, control, 0), " &
"66 (BC_7, P0_6, bidir, X, 65, 0, Z), " &
-- P0_5 IO group
"67 (BC_2, *, control, 0), " &
"68 (BC_7, P0_5, bidir, X, 67, 0, Z), " &
-- P0_4 IO group
"69 (BC_2, *, control, 0), " &
"70 (BC_7, P0_4, bidir, X, 69, 0, Z), " &
-- P0_3 IO group
"71 (BC_2, *, control, 0), " &
"72 (BC_7, P0_3, bidir, X, 71, 0, Z), " &
-- P0_2 IO group
"73 (BC_2, *, control, 0), " &
"74 (BC_7, P0_2, bidir, X, 73, 0, Z), " &
-- P0_1 IO group
"75 (BC_2, *, control, 0), " &
"76 (BC_7, P0_1, bidir, X, 75, 0, Z), " &
-- P0_0 IO group
"77 (BC_2, *, control, 0), " &
"78 (BC_7, P0_0, bidir, X, 77, 0, Z), " &
-- internal group
"79 (BC_0, *, internal, X), " &
"80 (BC_0, *, internal, X), " &
-- internal group
"81 (BC_0, *, internal, X), " &
"82 (BC_0, *, internal, X), " &
-- P12_3 IO group
"83 (BC_2, *, control, 0), " &
"84 (BC_7, P12_3, bidir, X, 83, 0, Z), " &
-- P12_2 IO group
"85 (BC_2, *, control, 0), " &
"86 (BC_7, P12_2, bidir, X, 85, 0, Z), " &
-- P15_3 IO group
"87 (BC_2, *, control, 0), " &
"88 (BC_7, P15_3, bidir, X, 87, 0, Z), " &
-- P15_2 IO group
"89 (BC_2, *, control, 0), " &
"90 (BC_7, P15_2, bidir, X, 89, 0, Z), " &
-- P12_1 IO group
"91 (BC_2, *, control, 0), " &
"92 (BC_7, P12_1, bidir, X, 91, 0, Z), " &
-- P12_0 IO group
"93 (BC_2, *, control, 0), " &
"94 (BC_7, P12_0, bidir, X, 93, 0, Z), " &
-- internal group
"95 (BC_0, *, internal, X), " &
"96 (BC_0, *, internal, X), " &
-- internal group
"97 (BC_0, *, internal, X), " &
"98 (BC_0, *, internal, X), " &
-- internal group
"99 (BC_0, *, internal, X), " &
"100 (BC_0, *, internal, X), " &
-- internal group
"101 (BC_0, *, internal, X), " &
"102 (BC_0, *, internal, X), " &
-- internal group
"103 (BC_0, *, internal, X), " &
"104 (BC_0, *, internal, X), " &
-- internal group
"105 (BC_0, *, internal, X), " &
"106 (BC_0, *, internal, X), " &
-- internal group
"107 (BC_0, *, internal, X), " &
"108 (BC_0, *, internal, X), " &
-- internal group
"109 (BC_0, *, internal, X), " &
"110 (BC_0, *, internal, X), " &
-- P15_1 IO group
"111 (BC_2, *, control, 0), " &
"112 (BC_7, P15_1, bidir, X, 111, 0, Z), " &
-- P15_0 IO group
"113 (BC_2, *, control, 0), " &
"114 (BC_7, P15_0, bidir, X, 113, 0, Z), " &
-- P15_6 O group
"115 (BC_0, *, internal, X), " &
"116 (BC_1, P15_7, output2, 1), " &
"117 (BC_0, *, internal, X), " &
"118 (BC_0, *, internal, X), " &
"119 (BC_0, *, internal, X), " &
"120 (BC_1, P15_6, output2, 1), " &
-- internal group
"121 (BC_0, *, internal, X), " &
"122 (BC_0, *, internal, X), " &
-- internal group
"123 (BC_0, *, internal, X), " &
"124 (BC_0, *, internal, X), " &
-- internal group
"125 (BC_0, *, internal, X), " &
"126 (BC_0, *, internal, X), " &
-- internal group
"127 (BC_0, *, internal, X), " &
"128 (BC_0, *, internal, X), " &
-- internal group
"129 (BC_0, *, internal, X), " &
"130 (BC_0, *, internal, X), " &
-- internal group
"131 (BC_0, *, internal, X), " &
"132 (BC_0, *, internal, X), " &
-- P1_7 IO group
"133 (BC_2, *, control, 0), " &
"134 (BC_7, P1_7, bidir, X, 133, 0, Z), " &
-- P1_6 IO group
"135 (BC_2, *, control, 0), " &
"136 (BC_7, P1_6, bidir, X, 135, 0, Z), " &
-- P1_5 IO group
"137 (BC_2, *, control, 0), " &
"138 (BC_7, P1_5, bidir, X, 137, 0, Z)";
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.15 - optional runbist description
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.16 - optional intest description
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.17 - optional BSDL extensions
--*****************************************************************************
--*****************************************************************************
--** IEEE Std 1149.1-2001 B.8.18 - optional design warning
--*****************************************************************************
attribute DESIGN_WARNING of CY8C3XXXX_XXX : entity is
"This CY8C3XXXX_XXX QFN48 BSDL file supports 1149.1 testing only after "&
"two of the following conditions are satisfied: "&
"1. The JTAG port is enabled. "&
"2. All IOs are pre-configured to drive out fast strong high/low. "&
"JTAG access can be enabled either through programming NV-Latch "&
"bits appropriately or through using test-port acquisition protocol. "&
"The IOs may be pre-configuration either by writing port "&
"configuration registers directly through a test port, or relying "&
"on a programmed boot sequence which does that to complete automatically. "&
"Testing other IO configurations requires changes to this file and "&
"the pre-configured IO configuration.";
-- You can put any other special care instructions here if needed.
end CY8C3XXXX_XXX;