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BSDL File: PSC_0 Download View details  


-- ***************************************************************************
-- 64-bit Intel(R) Xeon(TM) processor MP with 1MB L2 cache Core Boundary Scan
-- Descriptor Language (BSDL) Model, Version 2.0
-- 
--
-- ***************************************************************************
-- Information in this document is provided in connection with Intel products.
-- No license, express or implied, by estoppel or otherwise, to any
-- intellectual property rights is granted by this document. Except as
-- provided in Intel's Terms and Conditions of Sale for such products,
-- Intel assumes no liability whatsoever, and Intel disclaims any express or
-- implied warranty, relating to sale and/or use of Intel products including
-- liability or warranties relating to fitness for a particular purpose,
-- merchantability, or infringement of any patent, copyright or other
-- intellectual property right. Intel products are not intended for use in
-- medical, life saving, or life sustaining applications.
--
-- Intel may make changes to specifications and product descriptions at any
-- time, without notice.
--
-- The 64-bit Intel(R) Xeon(TM) processor MP with 1MB L2 cache may contain design
-- defects or errors known as errata which may cause the product to deviate
-- from published specifications. Current characterized errata are available
-- on request.
--
-- Contact your local Intel sales office or your distributor to obtain the
-- latest specifications and before placing your product order.
--
-- Copyright (c) Intel Corporation 2005. Third-party brands and names are the
-- property of their respective owners.
-- ***************************************************************************
--
entity PSC_0 is

  generic(PHYSICAL_PIN_MAP : string := "PSC_PGAN");

  port (
	A20M       : in      bit;			-- Compatibility 	- address 20 mask
	A          : inout   bit_vector(39 downto 3);	-- Address
	ADS        : inout   bit;			-- Request       	- address strobe
	ADSTB      : inout   bit_vector(1 downto 0);	-- Request		- address bus strobe
	AP         : inout   bit_vector(1 downto 0);	-- Address		- Address parity
	BCLK	   : in      bit_vector(1 downto 0);	-- Clock		- System bus clock		
	BINIT      : inout   bit;			-- Error	       	- bus initialization
	BNR        : inout   bit;			-- Arbitration   	- block next request
	BOOTSELECT : in      bit;			-- Analog Pin   	- Prevent Boot in non-compat systems	
	BPM        : inout   bit_vector(5 downto 0);	-- Diagnostic   	- proformance monitoring break points
	BPRI       : in      bit;			-- Arbitration   	- Priority agent bus arbitration
	BR0        : inout   bit;			-- Arbitration   	- symmetric agent bus input
	BR	   : in	     bit_vector(3 downto 1);	-- Arbitration		- symmetric agent bus I/O
	D          : inout   bit_vector(63 downto 0);	-- Data			- Data bus
	DBI        : inout   bit_vector(3 downto 0);	-- Data			- Data bus inversion
	DBSY       : inout   bit;			-- Data			- Data bus busy
	DEFER      : in      bit;			-- Snoop         	- Defer signal 
	DP         : inout   bit_vector(3 downto 0);	-- Data			- Data bus parity
	DRDY       : inout   bit;			-- Data			- Data phase data ready
	DSTBN      : inout   bit_vector(3 downto 0);	-- Data			- Data bus differential probe
	DSTBP      : inout   bit_vector(3 downto 0);	-- Data			- Data bus differential probe
	FERR       : out     bit;			-- Compatibility 	- floating point error
	FORCEPR	   : in	     bit;			-- Control		- Force power reduction
	HIT        : inout   bit;			-- Snoop         	- Snoop hit
	HITM       : inout   bit;			-- Snoop         	- Snoop hit modified
	IERR       : out     bit;			-- Error	       	- Internal processor error
	IGNNE      : in      bit;			-- Compatibility 	- Ignore numuric errors
	INIT       : in      bit;			-- Exec Control  	- Processor initialization
	LINT0      : in      bit;			-- APIC			- Local Interrupt,INT 	
	LINT1      : in      bit;			-- APIC 		- Local Interrupt,NMI
	LOCK       : inout   bit;			-- Arbitration   	- Locked transactions
	MCERR      : inout   bit;			-- Error	       	- Machine check error
	PROCHOT    : inout   bit;			-- Pwr/Clk       	- Thermal sensor
	PWRGOOD    : in      bit;			-- Pwr/Clk		- System Power Good
	RESET      : in      bit;			-- Control		- System Reset
	REQ        : inout   bit_vector(4 downto 0);	-- Request        	- request command
	RS         : in      bit_vector(2 downto 0);	-- Response status	
	RSP        : in      bit;			-- Response      	- Response status parity
	SMI        : in      bit;			-- Compatibility 	- System management interrupt
	STPCLK     : in      bit;			-- 		      	- Stop clock control
	TCK        : in      bit;			-- Diagnostic    	- tap clock
	TDI        : in      bit;			-- Diagnostic    	- tap data in
	TDO        : out     bit;			-- Diagnostic		- tap data out
	TESTBUS	   : in      bit;			-- Reserved		- TEST BUS Pin
	THERMTRIP  : out     bit;			-- Pwr/Clk       	- thermal sensor
	TMS        : in      bit;			-- Diagnostic    	- tap mode select
	TRDY       : in      bit;			-- Response      	- target ready   
	TRST       : in      bit;			-- Diagnostic    	- tap reset
	VIDPWRGD   : in	     bit			-- Control		- BSEL / VID stable
);

  use STD_1149_1_1994.all;
  use XEONMPL2_CELLS.all;

  attribute COMPONENT_CONFORMANCE of PSC_0 : entity is "STD_1149_1_1993" ;

  attribute PIN_MAP of PSC_0 : entity is PHYSICAL_PIN_MAP;

  constant PSC_PGAN : PIN_MAP_STRING :=

	"	A20M       : F27," &
	"	A          : (F16, F22, B6, C16, " &				-- A(36):A(39)
	"			C8, C9, A7, A6, B7, C11, D12, E13, B8, " &	-- A(35):A(27) 
	"			A9, D13, E14, C12, B11, B10, A10, F15, D15, " & -- A(26):A(18)
	"			D16, C14, C15, A12, B13, B14, B16, A13, D17," & -- A(17):A(9)  
	"			C17, A19, C18, B18, A20, A22), " &		-- A(8):A(3)
	"	ADS        : D19," &     
	"	ADSTB	   : (F14, F17), " &					-- ADSTB1, ADSTB0
	"	AP         : (D9, E10), " &					-- AP1, AP0
	"	BCLK	   : (W5, Y4),"  &					-- BCLK1, BCLK0
	"	BINIT      : F11," &     
	"	BNR        : F20," &
	"	BOOTSELECT : G7,"  &	
	"	BPM        : (E4, E8, F5, E7, F8, F6)," &			-- BPM5...BPM0
	"	BPRI       : D23,"  &
	"	BR0        : D20,"  &
	"	BR	   : (D10, E11, F12),"  &				-- BREQ3, BREQ2, BREQ1
	"	D          : (AB6, Y9, AA8, AC5, AC6, AE7, AD7, AC8," &				-- D63:D56
	"			AB10, AA10, AA11, AB13, AB12, AC14, AA14, AA13, AC9, AD8, " &	-- D55:D46
	"			AD10, AE9, AC11, AE10, AC12, AD11, AD14, AD13, "   & 		-- D45:D38
	"			AB15, AD18, AE13, AC17, AA16, AB16, AB17, AD19, "  & 		-- D37:D30
	"			AD21, AE20, AE22, AC21, AC20, AA18, AC23, AE23, "  & 		-- D29:D22
	"			AD24, AC24, AE25, AD25, AC26, AE26, AA19, AB19, "  & 		-- D21: D14
	"			AB22, AB20, AA21, AA22, AB23, AB25,"  &		 		-- D13:D8
	"			AB26, AA24, Y23, AD27, AA25, Y24, AA27, Y26)," & 		-- D7:D0
	" 	DBI	   : (AB9, AE12, AD22, AC27), "  &			-- DBI3... DBI0
	" 	DBSY       : F18,"  &
	"	DEFER      : C23,"  &
	"	DP         : (AE17, AC15, AE19, AC18), " &			-- DP3... DP0
	"	DRDY       : E18,"  &
	"	DSTBN      : (Y12, Y15, Y18, Y21), "  &				-- DSTBN3... DSTBN0
	" 	DSTBP      : (Y11, Y14, Y17, Y20), "  &				-- DSTBP3... DSTBP0
	"	FERR       : E27," &
	"	FORCEPR	   : A15," &
	" 	HIT        : E22," &
	" 	HITM       : A23," &
	" 	IERR       : E5,"  &
	" 	IGNNE      : C26," &
	" 	INIT       : D6,"  &
	" 	LINT0      : B24," &
	"	LINT1      : G23," &
	" 	LOCK       : A17," &
	" 	MCERR      : D7,"  &
	" 	PROCHOT    : B25," &
	"	PWRGOOD    : AB7," &
	"	RESET	   : Y8,"  &	
	" 	REQ        : (B22, C20, C21, B21, B19)," &			-- REQ4, REQ3, ... REQ0
	"	RS         : (F21, D22, E21),"  & 				-- RS2, RS1, RS0
	" 	RSP        : C6,"  &
	" 	SMI        : C27," &
	" 	STPCLK     : D4,"  &
	" 	TCK        : E24," &
	" 	TDI        : C24," &
	" 	TDO        : E25," &
	"	TESTBUS	   : A16," &
	" 	THERMTRIP  : F26," &
	" 	TMS        : A25," &	
	" 	TRDY       : E19," &
	" 	TRST       : F24," &
	"	VIDPWRGD   : B1"
  ;

--
-- Scan Port Identification
--

  attribute TAP_SCAN_IN    of TDI  : signal is true;
  attribute TAP_SCAN_MODE  of TMS  : signal is true;
  attribute TAP_SCAN_OUT   of TDO  : signal is true;
  attribute TAP_SCAN_RESET of TRST : signal is true;
  attribute TAP_SCAN_CLOCK of TCK  : signal is (16.0e6, both);

  attribute Instruction_Length of PSC_0: entity is 7;

  attribute Instruction_Opcode  of PSC_0: entity is

	" EXTEST   ( 0000000 ),                             		"  &
	" SAMPLE   ( 0000001 ),						"  &
	" IDCODE   ( 0000010 ),						"  &
	" CLAMP    ( 0000100 ),						"  &
	" RUNBIST  ( 0000111 ),						"  &
	" HIGHZ    ( 0001000 ),						"  &
	" BYPASS   ( 1111111 ),						"  &
	" Reserved ( 0000011, 0000101, 0000110, 0001001, 0001010,   	"  &
	"            0001011, 0001100, 0001101, 0001110, 0001111,   	"  &
	"            0010000, 0010001, 0010010, 0010011, 0010100,   	"  &
	"            0010101, 0010110, 0010111, 0011000, 0011001,   	"  &
	"            0011010, 0011011, 0011100, 0011101, 0011110,   	"  &
	"            0011111, 0100000, 0100001, 0100010, 0100011,   	"  &
	"            0100100, 0100101, 0100110, 0100111, 0101000,   	"  &
	"            0101001, 0101010, 0101011, 0101100, 0101101,   	"  &
	"            0101110, 0101111, 0110000, 0110001, 0110010,   	"  &
	"            0110011, 0110100, 0110101, 0110110, 0110111,   	"  &
	"            0111000, 0111001, 0111010, 0111011, 0111100,   	"  &
	"            0111101, 0111110, 0111111, 1000000, 1000001,   	"  &
	"            1000010, 1000011, 1000100, 1000101, 1000110,   	"  &
	"            1000111, 1001000, 1001001, 1001100, 1111110,   	"  &        
	"	     1111101, 1111100, 1111011, 1111010, 1111001,   	"  &
	"	     1111000, 1110111, 1001101, 1011110, 1011111,   	"  &
	"	     1011000, 1010000, 1010001, 1010010, 1010011,   	"  &
	"	     1010100, 1010101, 1010110, 1010111, 1011001,   	"  &
	"     	     1011010, 1011011, 1001011, 1001110, 1011100,   	"  &
	"	     1011101, 1110110, 1100000, 1100001, 1100010,   	"  &
	" 	     1100011) "  ;  

  attribute Instruction_Capture of PSC_0: entity is "0000001";
  attribute Instruction_Private of PSC_0: entity is "Reserved";

--
-- 64-bit Intel(R) Xeon(TM) processor MP with 1MB L2 cache IDCODE Register
--

  attribute Idcode_Register of PSC_0: entity is
	    "0001"             &     			-- Version, A-step
	    "1000001100000101" &     			-- Part number
	    "00000001001"      &     			-- Manufacturer's identity
	    "1";                     			-- Required by the 1149.1 standard

--
-- 64-bit Intel(R) Xeon(TM) processor MP with 1MB L2 cache Data Register Access
--

  attribute Register_Access of PSC_0: entity is

	    "BOUNDARY   (EXTEST, SAMPLE), "       &
	    "RUNBIST[1] (RUNBIST), "              &
	    "DEVICE_ID  (IDCODE), "               &
	    "BYPASS     (CLAMP, HIGHZ, BYPASS)";

--
-- 64-bit Intel(R) Xeon(TM) processor MP with 1MB L2 cache Boundary Scan cells
--
--    BS_4 : INPUT
--    BC_2 : OUTPUT
--    BS_G : GTL BIDIR/CONTROL Combo cell
--    BY_3 : Internal
--
--    PSC Boundary Register Description
--    Cell 0 is closest to TDO
--
  attribute BOUNDARY_LENGTH   of PSC_0: entity is 176;
  attribute Boundary_Register of PSC_0 : entity is
--           

 " 0   (BS_4,  LINT1,     input,     X                       ), " &
 " 1   (BS_4,  LINT0,     input,     X                       ), " &
 " 2   (BS_4,  BPRI,      input,     X                       ), " &
 " 3   (BS_4,  DEFER,     input,     X                       ), " &
 " 4   (BS_G,  HITM,      output2,   1,      4,  1,    Weak1 ), " &
 " 4   (BS_G,  HITM,      input,     1                       ), " &
 " 5   (BS_4,  RS(1),     input,     X                       ), " &
 " 6   (BS_G,  HIT,       output2,   1,      6,  1,    Weak1 ), " &
 " 6   (BS_G,  HIT,       input,     1                       ), " &
 " 7   (BS_4,  RS(2),     input,     X                       ), " &
 " 8   (BS_4,  RS(0),     input,     X                       ), " &
 " 9   (BS_G,  LOCK,      output2,   1,      9,  1,    Weak1 ), " &
 " 9   (BS_G,  LOCK,      input,     1                       ), " &
 " 10  (BS_G,  BR0,       output2,   1,     10,  1,    Weak1 ), " &
 " 10  (BS_G,  BR0,       input,     1                       ), " &
 " 11  (BS_4,  TRDY,      input,     X                       ), " &
 " 12  (BS_G,  ADS,       output2,   1,     12,  1,    Weak1 ), " &
 " 12  (BS_G,  ADS,       input,     1                       ), " &
 " 13  (BS_G,  BNR,       output2,   1,     13,  1,    Weak1 ), " &
 " 13  (BS_G,  BNR,       input,     1                       ), " &
 " 14  (BS_G,  DBSY,      output2,   1,     14,  1,    Weak1 ), " &
 " 14  (BS_G,  DBSY,      input,     1                       ), " &
 " 15  (BS_G,  DRDY,      output2,   1,     15,  1,    Weak1 ), " &
 " 15  (BS_G,  DRDY,      input,     1                       ), " &
 " 16  (BS_G,  REQ(4),    output2,   1,     16,  1,    Weak1 ), " &
 " 16  (BS_G,  REQ(4),    input,     1                       ), " &
 " 17  (BS_G,  REQ(3),    output2,   1,     17,  1,    Weak1 ), " &
 " 17  (BS_G,  REQ(3),    input,     1                       ), " &
 " 18  (BS_G,  REQ(2),    output2,   1,     18,  1,    Weak1 ), " &
 " 18  (BS_G,  REQ(2),    input,     1                       ), " &
 " 19  (BS_G,  REQ(1),    output2,   1,     19,  1,    Weak1 ), " &
 " 19  (BS_G,  REQ(1),    input,     1                       ), " &
 " 20  (BS_G,  REQ(0),    output2,   1,     20,  1,    Weak1 ), " &
 " 20  (BS_G,  REQ(0),    input,     1                       ), " &
 " 21  (BS_G,  A(3),      output2,   1,     21,  1,    Weak1 ), " &
 " 21  (BS_G,  A(3),      input,     1                       ), " &
 " 22  (BS_G,  A(4),      output2,   1,     22,  1,    Weak1 ), " &
 " 22  (BS_G,  A(4),      input,     1                       ), " &
 " 23  (BS_G,  A(5),      output2,   1,     23,  1,    Weak1 ), " &
 " 23  (BS_G,  A(5),      input,     1                       ), " &
 " 24  (BS_G,  A(6),      output2,   1,     24,  1,    Weak1 ), " &
 " 24  (BS_G,  A(6),      input,     1                       ), " &
 " 25  (BS_G,  A(7),      output2,   1,     25,  1,    Weak1 ), " &
 " 25  (BS_G,  A(7),      input,     1                       ), " &
 " 26  (BS_G,  A(36),     output2,   1,     26,  1,    Weak1 ), " &
 " 26  (BS_G,  A(36),     input,     1                       ), " &
 " 27  (BS_G,  ADSTB(0),  output2,   1,     27,  1,    Weak1 ), " &
 " 27  (BS_G,  ADSTB(0),  input,     1                       ), " &
 " 28  (BS_G,  A(37),     output2,   1,     28,  1,    Weak1 ), " &
 " 28  (BS_G,  A(37),     input,     1                       ), " &
 " 29  (BS_G,  A(8),      output2,   1,     29,  1,    Weak1 ), " &
 " 29  (BS_G,  A(8),      input,     1                       ), " &
 " 30  (BS_G,  A(9),      output2,   1,     30,  1,    Weak1 ), " &
 " 30  (BS_G,  A(9),      input,     1                       ), " &
 " 31  (BS_G,  A(10),     output2,   1,     31,  1,    Weak1 ), " &
 " 31  (BS_G,  A(10),     input,     1                       ), " &
 " 32  (BS_G,  A(11),     output2,   1,     32,  1,    Weak1 ), " &
 " 32  (BS_G,  A(11),     input,     1                       ), " &
 " 33  (BS_G,  A(13),     output2,   1,     33,  1,    Weak1 ), " &
 " 33  (BS_G,  A(13),     input,     1                       ), " &
 " 34  (BS_G,  A(12),     output2,   1,     34,  1,    Weak1 ), " &
 " 34  (BS_G,  A(12),     input,     1                       ), " &
 " 35  (BS_G,  A(14),     output2,   1,     35,  1,    Weak1 ), " &
 " 35  (BS_G,  A(14),     input,     1                       ), " &
 " 36  (BS_G,  A(15),     output2,   1,     36,  1,    Weak1 ), " &
 " 36  (BS_G,  A(15),     input,     1                       ), " &
 " 37  (BS_G,  A(16),     output2,   1,     37,  1,    Weak1 ), " &
 " 37  (BS_G,  A(16),     input,     1                       ), " &
 " 38  (BS_G,  A(17),     output2,   1,     38,  1,    Weak1 ), " &
 " 38  (BS_G,  A(17),     input,     1                       ), " &
 " 39  (BS_G,  A(18),     output2,   1,     39,  1,    Weak1 ), " &
 " 39  (BS_G,  A(18),     input,     1                       ), " &
 " 40  (BS_G,  A(19),     output2,   1,     40,  1,    Weak1 ), " &
 " 40  (BS_G,  A(19),     input,     1                       ), " &
 " 41  (BS_G,  A(20),     output2,   1,     41,  1,    Weak1 ), " &
 " 41  (BS_G,  A(20),     input,     1                       ), " &
 " 42  (BS_G,  A(21),     output2,   1,     42,  1,    Weak1 ), " &
 " 42  (BS_G,  A(21),     input,     1                       ), " &
 " 43  (BS_G,  A(22),     output2,   1,     43,  1,    Weak1 ), " &
 " 43  (BS_G,  A(22),     input,     1                       ), " &
 " 44  (BS_G,  A(23),     output2,   1,     44,  1,    Weak1 ), " &
 " 44  (BS_G,  A(23),     input,     1                       ), " &
 " 45  (BS_G,  A(24),     output2,   1,     45,  1,    Weak1 ), " &
 " 45  (BS_G,  A(24),     input,     1                       ), " &
 " 46  (BS_G,  A(25),     output2,   1,     46,  1,    Weak1 ), " &
 " 46  (BS_G,  A(25),     input,     1                       ), " &
 " 47  (BS_G,  A(26),     output2,   1,     47,  1,    Weak1 ), " &
 " 47  (BS_G,  A(26),     input,     1                       ), " &
 " 48  (BS_G,  A(38),     output2,   1,     48,  1,    Weak1 ), " &
 " 48  (BS_G,  A(38),     input,     1                       ), " &
 " 49  (BS_G,  ADSTB(1),  output2,   1,     49,  1,    Weak1 ), " &
 " 49  (BS_G,  ADSTB(1),  input,     1                       ), " &
 " 50  (BS_G,  A(39),     output2,   1,     50,  1,    Weak1 ), " &
 " 50  (BS_G,  A(39),     input,     1                       ), " &
 " 51  (BS_G,  A(27),     output2,   1,     51,  1,    Weak1 ), " &
 " 51  (BS_G,  A(27),     input,     1                       ), " &
 " 52  (BS_G,  A(28),     output2,   1,     52,  1,    Weak1 ), " &
 " 52  (BS_G,  A(28),     input,     1                       ), " &
 " 53  (BS_G,  A(29),     output2,   1,     53,  1,    Weak1 ), " &
 " 53  (BS_G,  A(29),     input,     1                       ), " &
 " 54  (BS_G,  A(30),     output2,   1,     54,  1,    Weak1 ), " &
 " 54  (BS_G,  A(30),     input,     1                       ), " &
 " 55  (BS_G,  A(31),     output2,   1,     55,  1,    Weak1 ), " &
 " 55  (BS_G,  A(31),     input,     1                       ), " &
 " 56  (BS_G,  A(32),     output2,   1,     56,  1,    Weak1 ), " &
 " 56  (BS_G,  A(32),     input,     1                       ), " &
 " 57  (BS_G,  A(33),     output2,   1,     57,  1,    Weak1 ), " &
 " 57  (BS_G,  A(33),     input,     1                       ), " &
 " 58  (BS_G,  A(34),     output2,   1,     58,  1,    Weak1 ), " &
 " 58  (BS_G,  A(34),     input,     1                       ), " &
 " 59  (BS_G,  A(35),     output2,   1,     59,  1,    Weak1 ), " &
 " 59  (BS_G,  A(35),     input,     1                       ), " &
 " 60  (BS_4,  BR(1),	  input,     1                       ), " &
 " 61  (BS_4,  BR(2),     input,     1                       ), " &
 " 62  (BS_4,  BR(3),     input,     1                       ), " &
 " 63  (BS_G,  AP(1),     output2,   1,     63,  1,    Weak1 ), " &
 " 63  (BS_G,  AP(1),     input,     1                       ), " &
 " 64  (BS_G,  AP(0),     output2,   1,     64,  1,    Weak1 ), " &
 " 64  (BS_G,  AP(0),     input,     1                       ), " &
 " 65  (BS_4,  RSP,       input,     X                       ), " &
 " 66  (BS_G,  BINIT,     output2,   1,     66,  1,    Weak1 ), " &
 " 66  (BS_G,  BINIT,     input,     1                       ), " &
 " 67  (BS_G,  MCERR,     output2,   1,     67,  1,    Weak1 ), " &
 " 67  (BS_G,  MCERR,     input,     1                       ), " &
 " 68  (BS_4,  INIT,      input,     X                       ), " &
 " 69  (BS_4,  STPCLK,    input,     X                       ), " &
 " 70  (BX_2,  IERR,      output2,   1,     70,  1,    Weak1 ), " &
 " 71  (BS_G,  BPM(5),    output2,   1,     71,  1,    Weak1 ), " &
 " 71  (BS_G,  BPM(5),    input,     1                       ), " &
 " 72  (BS_G,  BPM(4),    output2,   1,     72,  1,    Weak1 ), " &
 " 72  (BS_G,  BPM(4),    input,     1                       ), " &
 " 73  (BS_G,  BPM(3),    output2,   1,     73,  1,    Weak1 ), " &
 " 73  (BS_G,  BPM(3),    input,     1                       ), " &
 " 74  (BS_G,  BPM(2),    output2,   1,     74,  1,    Weak1 ), " &
 " 74  (BS_G,  BPM(2),    input,     1                       ), " &
 " 75  (BS_G,  BPM(1),    output2,   1,     75,  1,    Weak1 ), " &
 " 75  (BS_G,  BPM(1),    input,     1                       ), " &
 " 76  (BS_G,  BPM(0),    output2,   1,     76,  1,    Weak1 ), " &
 " 76  (BS_G,  BPM(0),    input,     1                       ), " &
 " 77  (BS_4,  BOOTSELECT,input,     X                       ), " &
 " 78  (BS_4,  VIDPWRGD,  input,     0                       ), " &
 " 79  (BY_3,  *,         internal,  1                       ), " &
 " 80  (BY_3,  *,         internal,  1                       ), " &
 " 81  (BY_3,  *,         internal,  1                       ), " &
 " 82  (BS_4,  BCLK(1),   input,     1                       ), " &
 " 83  (BS_4,  BCLK(0),   input,     1                       ), " &
 " 84  (BS_4,  PWRGOOD,   input,     1                       ), " &
 " 85  (BS_4,  RESET,     input,     1                       ), " &
 " 86  (BY_3,  *,         internal,  1                       ), " &
 " 87  (BS_G,  D(63),     output2,   1,     87,  1,    Weak1 ), " &
 " 87  (BS_G,  D(63),     input,     1                       ), " &
 " 88  (BS_G,  D(62),     output2,   1,     88,  1,    Weak1 ), " &
 " 88  (BS_G,  D(62),     input,     1                       ), " &
 " 89  (BS_G,  D(61),     output2,   1,     89,  1,    Weak1 ), " &
 " 89  (BS_G,  D(61),     input,     1                       ), " &
 " 90  (BS_G,  D(60),     output2,   1,     90,  1,    Weak1 ), " &
 " 90  (BS_G,  D(60),     input,     1                       ), " &
 " 91  (BS_G,  D(59),     output2,   1,     91,  1,    Weak1 ), " &
 " 91  (BS_G,  D(59),     input,     1                    ), " &
 " 92  (BS_G,  D(58),     output2,   1,     92,  1,    Weak1 ), " &
 " 92  (BS_G,  D(58),     input,     1                    ), " &
 " 93  (BS_G,  D(57),     output2,   1,     93,  1,    Weak1 ), " &
 " 93  (BS_G,  D(57),     input,     1                    ), " &
 " 94  (BS_G,  D(56),     output2,   1,     94,  1,    Weak1 ), " &
 " 94  (BS_G,  D(56),     input,     1                    ), " &
 " 95  (BS_G,  DSTBN(3),  output2,   1,     95,  1,    Weak1 ), " &
 " 95  (BS_G,  DSTBN(3),  input,     1                    ), " &
 " 96  (BS_G,  DSTBP(3),  output2,   1,     96,  1,    Weak1 ), " &
 " 96  (BS_G,  DSTBP(3),  input,     1                    ), " &
 " 97  (BS_G,  DBI(3),    output2,   1,     97,  1,    Weak1 ), " &
 " 97  (BS_G,  DBI(3),    input,     1                    ), " &
 " 98  (BS_G,  D(55),     output2,   1,     98,  1,    Weak1 ), " &
 " 98  (BS_G,  D(55),     input,     1                    ), " &
 " 99  (BS_G,  D(54),     output2,   1,     99,  1,    Weak1 ), " &
 " 99  (BS_G,  D(54),     input,     1                    ), " &
 " 100 (BS_G,  D(53),     output2,   1,     100,  1,    Weak1 ), " &
 " 100 (BS_G,  D(53),     input,     1                    ), " &
 " 101 (BS_G,  D(51),     output2,   1,     101,  1,    Weak1 ), " &
 " 101 (BS_G,  D(51),     input,     1                    ), " &
 " 102 (BS_G,  D(52),     output2,   1,     102,  1,    Weak1 ), " &
 " 102 (BS_G,  D(52),     input,     1                    ), " &
 " 103 (BS_G,  D(50),     output2,   1,     103,  1,    Weak1 ), " &
 " 103 (BS_G,  D(50),     input,     1                    ), " &
 " 104 (BS_G,  D(49),     output2,   1,     104,  1,    Weak1 ), " &
 " 104 (BS_G,  D(49),     input,     1                    ), " &
 " 105 (BS_G,  D(48),     output2,   1,     105,  1,    Weak1 ), " &
 " 105 (BS_G,  D(48),     input,     1                    ), " &
 " 106 (BS_G,  D(47),     output2,   1,     106,  1,    Weak1 ), " &
 " 106 (BS_G,  D(47),     input,     1                    ), " &
 " 107 (BS_G,  D(46),     output2,   1,     107,  1,    Weak1 ), " &
 " 107 (BS_G,  D(46),     input,     1                    ), " &
 " 108 (BS_G,  D(45),     output2,   1,     108,  1,    Weak1 ), " &
 " 108 (BS_G,  D(45),     input,     1                    ), " &
 " 109 (BS_G,  D(44),     output2,   1,     109,  1,    Weak1 ), " &
 " 109 (BS_G,  D(44),     input,     1                    ), " &
 " 110 (BS_G,  D(43),     output2,   1,     110,  1,    Weak1 ), " &
 " 110 (BS_G,  D(43),     input,     1                    ), " &
 " 111 (BS_G,  D(42),     output2,   1,     111,  1,    Weak1 ), " &
 " 111 (BS_G,  D(42),     input,     1                    ), " &
 " 112 (BS_G,  D(41),     output2,   1,     112,  1,    Weak1 ), " &
 " 112 (BS_G,  D(41),     input,     1                    ), " &
 " 113 (BS_G,  D(40),     output2,   1,     113,  1,    Weak1 ), " &
 " 113 (BS_G,  D(40),     input,     1                    ), " &
 " 114 (BS_G,  DSTBN(2),  output2,   1,     114,  1,    Weak1 ), " &
 " 114 (BS_G,  DSTBN(2),  input,     1                    ), " &
 " 115 (BS_G,  DSTBP(2),  output2,   1,     115,  1,    Weak1 ), " &
 " 115 (BS_G,  DSTBP(2),  input,     1                    ), " &
 " 116 (BS_G,  DBI(2),    output2,   1,     116,  1,    Weak1 ), " &
 " 116 (BS_G,  DBI(2),    input,     1                    ), " &
 " 117 (BS_G,  D(39),     output2,   1,     117,  1,    Weak1 ), " &
 " 117 (BS_G,  D(39),     input,     1                    ), " &
 " 118 (BS_G,  D(38),     output2,   1,     118,  1,    Weak1 ), " &
 " 118 (BS_G,  D(38),     input,     1                    ), " &
 " 119 (BS_G,  D(37),     output2,   1,     119,  1,    Weak1 ), " &
 " 119 (BS_G,  D(37),     input,     1                    ), " &
 " 120 (BS_G,  D(35),     output2,   1,     120,  1,    Weak1 ), " &
 " 120 (BS_G,  D(35),     input,     1                    ), " &
 " 121 (BS_G,  D(36),     output2,   1,     121,  1,    Weak1 ), " &
 " 121 (BS_G,  D(36),     input,     1                    ), " &
 " 122 (BS_G,  D(34),     output2,   1,     122,  1,    Weak1 ), " &
 " 122 (BS_G,  D(34),     input,     1                    ), " &
 " 123 (BS_G,  D(33),     output2,   1,     123,  1,    Weak1 ), " &
 " 123 (BS_G,  D(33),     input,     1                    ), " &
 " 124 (BS_G,  D(32),     output2,   1,     124,  1,    Weak1 ), " &
 " 124 (BS_G,  D(32),     input,     1                    ), " &
 " 125 (BS_G,  DP(3),     output2,   1,     125,  1,    Weak1 ), " &
 " 125 (BS_G,  DP(3),     input,     1                    ), " &
 " 126 (BS_G,  DP(2),     output2,   1,     126,  1,    Weak1 ), " &
 " 126 (BS_G,  DP(2),     input,     1                    ), " &
 " 127 (BS_G,  DP(1),     output2,   1,     127,  1,    Weak1 ), " &
 " 127 (BS_G,  DP(1),     input,     1                    ), " &
 " 128 (BS_G,  DP(0),     output2,   1,     128,  1,    Weak1 ), " &
 " 128 (BS_G,  DP(0),     input,     1                    ), " &
 " 129 (BS_G,  D(31),     output2,   1,     129,  1,    Weak1 ), " &
 " 129 (BS_G,  D(31),     input,     1                    ), " &
 " 130 (BS_G,  D(30),     output2,   1,     130,  1,    Weak1 ), " &
 " 130 (BS_G,  D(30),     input,     1                    ), " &
 " 131 (BS_G,  D(29),     output2,   1,     131,  1,    Weak1 ), " &
 " 131 (BS_G,  D(29),     input,     1                    ), " &
 " 132 (BS_G,  D(28),     output2,   1,     132,  1,    Weak1 ), " &
 " 132 (BS_G,  D(28),     input,     1                    ), " &
 " 133 (BS_G,  D(27),     output2,   1,     133,  1,    Weak1 ), " &
 " 133 (BS_G,  D(27),     input,     1                    ), " &
 " 134 (BS_G,  D(26),     output2,   1,     134,  1,    Weak1 ), " &
 " 134 (BS_G,  D(26),     input,     1                    ), " &
 " 135 (BS_G,  D(25),     output2,   1,     135,  1,    Weak1 ), " &
 " 135 (BS_G,  D(25),     input,     1                    ), " &
 " 136 (BS_G,  D(24),     output2,   1,     136,  1,    Weak1 ), " &
 " 136 (BS_G,  D(24),     input,     1                    ), " &
 " 137 (BS_G,  DSTBN(1),  output2,   1,     137,  1,    Weak1 ), " &
 " 137 (BS_G,  DSTBN(1),  input,     1                    ), " &
 " 138 (BS_G,  DSTBP(1),  output2,   1,     138,  1,    Weak1 ), " &
 " 138 (BS_G,  DSTBP(1),  input,     1                    ), " &
 " 139 (BS_G,  DBI(1),    output2,   1,     139,  1,    Weak1 ), " &
 " 139 (BS_G,  DBI(1),    input,     1                    ), " &
 " 140 (BS_G,  D(23),     output2,   1,     140,  1,    Weak1 ), " &
 " 140 (BS_G,  D(23),     input,     1                    ), " &
 " 141 (BS_G,  D(22),     output2,   1,     141,  1,    Weak1 ), " &
 " 141 (BS_G,  D(22),     input,     1                    ), " &
 " 142 (BS_G,  D(21),     output2,   1,     142,  1,    Weak1 ), " &
 " 142 (BS_G,  D(21),     input,     1                    ), " &
 " 143 (BS_G,  D(19),     output2,   1,     143,  1,    Weak1 ), " &
 " 143 (BS_G,  D(19),     input,     1                    ), " &
 " 144 (BS_G,  D(20),     output2,   1,     144,  1,    Weak1 ), " &
 " 144 (BS_G,  D(20),     input,     1                    ), " &
 " 145 (BS_G,  D(18),     output2,   1,     145,  1,    Weak1 ), " &
 " 145 (BS_G,  D(18),     input,     1                    ), " &
 " 146 (BS_G,  D(17),     output2,   1,     146,  1,    Weak1 ), " &
 " 146 (BS_G,  D(17),     input,     1                    ), " &
 " 147 (BS_G,  D(16),     output2,   1,     147,  1,    Weak1 ), " &
 " 147 (BS_G,  D(16),     input,     1                    ), " &
 " 148 (BS_G,  D(15),     output2,   1,     148,  1,    Weak1 ), " &
 " 148 (BS_G,  D(15),     input,     1                    ), " &
 " 149 (BS_G,  D(14),     output2,   1,     149,  1,    Weak1 ), " &
 " 149 (BS_G,  D(14),     input,     1                    ), " &
 " 150 (BS_G,  D(13),     output2,   1,     150,  1,    Weak1 ), " &
 " 150 (BS_G,  D(13),     input,     1                    ), " &
 " 151 (BS_G,  D(12),     output2,   1,     151,  1,    Weak1 ), " &
 " 151 (BS_G,  D(12),     input,     1                    ), " &
 " 152 (BS_G,  D(11),     output2,   1,     152,  1,    Weak1 ), " &
 " 152 (BS_G,  D(11),     input,     1                    ), " &
 " 153 (BS_G,  D(10),     output2,   1,     153,  1,    Weak1 ), " &
 " 153 (BS_G,  D(10),     input,     1                    ), " &
 " 154 (BS_G,  D(9),      output2,   1,     154,  1,    Weak1 ), " &
 " 154 (BS_G,  D(9),      input,     1                    ), " &
 " 155 (BS_G,  D(8),      output2,   1,     155,  1,    Weak1 ), " &
 " 155 (BS_G,  D(8),      input,     1                    ), " &
 " 156 (BS_G,  DSTBN(0),  output2,   1,     156,  1,    Weak1 ), " &
 " 156 (BS_G,  DSTBN(0),  input,     1                    ), " &
 " 157 (BS_G,  DSTBP(0),  output2,   1,     157,  1,    Weak1 ), " &
 " 157 (BS_G,  DSTBP(0),  input,     1                    ), " &
 " 158 (BS_G,  DBI(0),    output2,   1,     158,  1,    Weak1 ), " &
 " 158 (BS_G,  DBI(0), 	  input,     1                    ), " &
 " 159 (BS_G,  D(7),      output2,   1,     159,  1,    Weak1 ), " &
 " 159 (BS_G,  D(7),      input,     1                    ), " &
 " 160 (BS_G,  D(6),      output2,   1,     160,  1,    Weak1 ), " &
 " 160 (BS_G,  D(6),      input,     1                    ), " &
 " 161 (BS_G,  D(5),      output2,   1,     161,  1,    Weak1 ), " &
 " 161 (BS_G,  D(5),      input,     1                    ), " &
 " 162 (BS_G,  D(3),      output2,   1,     162,  1,    Weak1 ), " &
 " 162 (BS_G,  D(3),      input,     1                    ), " &
 " 163 (BS_G,  D(4),      output2,   1,     163,  1,    Weak1 ), " &
 " 163 (BS_G,  D(4),      input,     1                    ), " &
 " 164 (BS_G,  D(2),      output2,   1,     164,  1,    Weak1 ), " &
 " 164 (BS_G,  D(2),      input,     1                    ), " &
 " 165 (BS_G,  D(1),      output2,   1,     165,  1,    Weak1 ), " &
 " 165 (BS_G,  D(1),      input,     1                    ), " &
 " 166 (BS_G,  D(0),      output2,   1,     166,  1,    Weak1 ), " &
 " 166 (BS_G,  D(0),      input,     1                       ), " &
 " 167 (BS_4,  FORCEPR,   input,     X                       ), " &
 " 168 (BS_4,  TESTBUS,   input,     X                       ), " &
 " 169 (BY_3,  *,         internal,  1                       ), " &
 " 170 (BX_2,  FERR,      output2,   1,    170,  1,    Weak1 ), " &
 " 171 (BS_4,  A20M,      input,     X                       ), " &
 " 172 (BS_4,  SMI,       input,     X                       ), " &
 " 173 (BS_4,  IGNNE,     input,     X                       ), " &
 " 174 (BX_2,  THERMTRIP, output2,   1,    174,  1,    Weak1 ), " &
 " 175 (BS_G,  PROCHOT,   output2,   1,    175,  1,    Weak1 ), " &
 " 175 (BS_G,  PROCHOT,   input,     1 			  )  " ; 

end PSC_0;

This library contains 7714 BSDL files (for 6086 distinct entities) from 64 vendors
Last BSDL model (CY7C1512KV18) was added on Sep 15, 2017 14:30
info@bsdl.info