--$ XILINX$RCSfile: xcr3128a_vq100.bsd,v $
--$ XILINX$Revision: 1.2 $
--
-- BSDL file for device XCR3128a, package VQ100
-- Xilinx, Inc. $State: ADVANCED $ $Date: 2005-10-06 15:21:34-07 $
-- Generated by
--
-- IMPORTANT NOTE WARNING !!
-- ****************************************************************
-- Boundary registers as called out by this file do not exist!
-- They must be described for BSDL Compliance. Extest and
-- Preload commands do not exist nor function. If either of
-- those commands are selected, the bypass register will be
-- used.
--
-- For technical support, contact Xilinx at
--
-- http://support.xilinx.com
--
-- or as follow:
-- North America 1-800-255-7778 hotline@xilinx.com
-- United Kingdom (44) 1932 820821 ukhelp@xilinx.com
-- France (33) 1 3463 0100 frhelp@xilinx.com
-- Germany (49) 89 991 54930 dlhelp@xilinx.com
-- Japan (81) 3-3297-9163 jhotline@xilinx.com
--
entity XCR3128A_VQ100 is
generic (PHYSICAL_PIN_MAP : string := "xcr3128a");
port (din : linkage bit_vector (0 to 3); -- Tim pin type IN
TDI : in bit; -- Tim pin type TDI
TMS : in bit; -- Tim pin type TMS
TCK : in bit; -- Tim pin type TCK
TDO : out bit; -- Tim pin type TDO
ioA : linkage bit_vector (0 to 9); -- Tim pin type IOO
ioB : linkage bit_vector (0 to 8); -- Tim pin type IOO
ioC : linkage bit_vector (0 to 8); -- Tim pin type IOO
ioD : linkage bit_vector (0 to 9); -- Tim pin type IOO
ioE : linkage bit_vector (0 to 9); -- Tim pin type IOO
ioF : linkage bit_vector (0 to 8); -- Tim pin type IOO
ioG : linkage bit_vector (0 to 8); -- Tim pin type IOO
ioH : linkage bit_vector (0 to 9); -- Tim pin type IOO
Vcc : linkage bit_vector (1 to 8);
Gnd : linkage bit_vector (1 to 8)
);
use STD_1149_1_1994.ALL;
attribute COMPONENT_CONFORMANCE of XCR3128A_VQ100 : entity is
"std_1149_1_1993";
attribute PIN_MAP of XCR3128A_VQ100 : entity is PHYSICAL_PIN_MAP;
constant xcr3128a : PIN_MAP_STRING :=
"din : ( 87, 89, 88, 90)," &
"TDI : 4," &
"TMS : 15," &
"TCK : 62," &
"TDO : 73," &
"ioA : ( 2, 1, 100, 99, 98, 97, 96, 94, 93, 92), " &
"ioB : ( 14, 13, 12, 10, 9, 8, 7, 6, 5), " &
"ioC : ( 25, 24, 23, 22, 21, 20, 19, 17, 16), " &
"ioD : ( 37, 36, 35, 33, 32, 31, 30, 29, 28, 27), " &
"ioE : ( 40, 41, 42, 44, 45, 46, 47, 48, 49, 50), " &
"ioF : ( 52, 53, 54, 55, 56, 57, 58, 60, 61), " &
"ioG : ( 63, 64, 65, 67, 68, 69, 70, 71, 72), " &
"ioH : ( 75, 76, 77, 78, 79, 80, 81, 83, 84, 85), " &
"Vcc : ( 3, 18, 34, 39, 51, 66, 82, 91), " &
"Gnd : ( 11, 26, 38, 43, 59, 74, 86, 95) ";
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, both);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
-- Instruction Register Definitions
attribute INSTRUCTION_LENGTH of XCR3128A_VQ100 : entity is 4;
attribute INSTRUCTION_OPCODE of XCR3128A_VQ100 : entity is
"SAMPLE (0010)," &
"EXTEST (0000)," &
"IDCODE (0001)," &
"BYPASS (1111)," &
"ENABLEOTF (1000)," &
"ENABLE (1001)," &
"ERASE (1010)," &
"PROGRAM (1011)," &
"VERIFY (1100)," &
"INIT (1101)";
attribute INSTRUCTION_CAPTURE of XCR3128A_VQ100 : entity is "0001";
attribute IDCODE_REGISTER of XCR3128A_VQ100 : entity is
"XXXX" & -- Version
"000" & -- Architecture
"010" & -- Technology
"001001" & -- Part number
"1" & -- Voltage
"100" & -- Package
"00000010101" & -- Manufacturer
"1"; -- mandatory
attribute REGISTER_ACCESS of XCR3128A_VQ100 : entity is
"DEVICE_ID (IDCODE)," &
"BOUNDARY (SAMPLE)," &
"BYPASS (BYPASS)," &
"MISR[5] (ENABLEOTF)," &
"MISR[5] (ENABLE)," &
"MISR[5] (ERASE)," &
"MISR[5] (PROGRAM)," &
"MISR[5] (VERIFY)," &
"BYPASS (INIT)";
attribute BOUNDARY_LENGTH of XCR3128A_VQ100 : entity is 1;
attribute BOUNDARY_REGISTER of XCR3128A_VQ100 : entity is
--
-- num cell port function safe [ccell disval rslt]
--
"0 (BC_1, *, INTERNAL, X)";
end XCR3128A_VQ100;