BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: CY7C4122KV13

--*******************************************************************************************************
--**  Copyright (c) 2013 Cypress Semiconductor
--**  All rights reserved.
--**							
--**  File Name:     	CY7C4122KV13_x18_361.bsdl	
--**  Release:	 	    1.0							   
--**  Last Updated:  	January 14, 2014
--**  Revision History: 
--**                    1.0 -- New BSDL model; 
--**                    
--**  Written by:       Cypress MPD Applications
--**  Queries ?:    	Contact Cypress MPD Applications
--**  Note:         	This part is fully compliant with IEEE standard 1149.1
--**  Part #:			CY7C4122KV13
--**  Package:			361 Ball FCBGA
--**  Function:			8M x 18 144-MBIT QDR(TM)-IV XP SRAM, BSDL file for JTAG
--**
--**	Ref CY7C4122KV13 Datasheet at www.cypress.com/--**
--**    Note: Boundary scan register has output enable control bits located at Bit#49 and Bit#50.
--**          Based on the port configuration Bit#49 and Bit#50 need to change as below.  
--**          Port B Write only & Port A Read only --> Bit#49 = 0 & Bit#50 = 1
--**          Port B Disabled & Port A Enabled     --> Bit#49 = 0 & Bit#50 = 1
--**          Port B Enabled & Port A Enabled      --> Bit#49 = 1 & Bit#50 = 1
--**          Port B Disabled & Port A Disabled    --> (Not supported)
--**
--*******************************************************************************************************

entity CY7C4122KV13 is
	generic (PHYSICAL_PIN_MAP : string := "FCBGA");

	port  (
	    CK:		 in		   bit;
		CK_n:	 in		   bit;		
		A: 		 in		   bit_vector(0 to 21);
		NC:      linkage   bit_vector(0 to 38);
		AINV:    in    	   bit;
		LDA_n:   in    	   bit;
		LDB_n:   in    	   bit;
		RWA_n:   in    	   bit;
		RWB_n:   in    	   bit;
		AP:      in    	   bit;
		PE_n:	 buffer    bit;
		DKA:     in		   bit_vector(0 to 1);
		DKA_n:   in		   bit_vector(0 to 1);
		DKB:     in		   bit_vector(0 to 1);
		DKB_n:   in		   bit_vector(0 to 1);
		QKA:     buffer	   bit_vector(0 to 1);
		QKA_n:   buffer	   bit_vector(0 to 1);
		QKB:     buffer	   bit_vector(0 to 1);
		QKB_n:   buffer	   bit_vector(0 to 1);
		DQA:     inout     bit_vector(0 to 17);
		DQB:     inout     bit_vector(0 to 17);
		DINVA:   inout     bit_vector(0 to 1);
		DINVB:   inout     bit_vector(0 to 1);
		QVLDA:	 buffer    bit_vector(0 to 1);
		QVLDB:	 buffer    bit_vector(0 to 1);
		CFG_n:   in		   bit;
		RST_n:   in		   bit;
		LBK_n:   in        bit_vector(0 to 1);
		TMS: 	 in    	   bit;
		TDI: 	 in    	   bit;
		TCK: 	 in    	   bit;
		TDO: 	 out   	   bit;
		TRST_n:  in    	   bit;
		DNU:     linkage   bit;
		VREF:	 linkage   bit_vector(0 to 5);
		VDD: 	 linkage   bit_vector(0 to 43);
		VDDQ: 	 linkage   bit_vector(0 to 63);
		VSS: 	 linkage   bit_vector(0 to 105)
		);

	use STD_1149_1_2001.all;

	attribute COMPONENT_CONFORMANCE of CY7C4122KV13 : entity is "STD_1149_1_1993";

	attribute PIN_MAP of CY7C4122KV13 : entity is PHYSICAL_PIN_MAP;

		constant  FCBGA:PIN_MAP_STRING:=
			"CK:J10, " &--Address/Command Input Clock
			"CK_n:K10, " &--Address/Command Input Clock
			"A:(F10,G10,N10,G7,G13,J7,J13,L7,L13,N7, 	" &
			"N13,M8,M12,F8,F12,P8,P12,L9,L11,J9,J11,G9), " &	--Address
			"NC:(G11,N9,N11,M17,M15,L18,L16,V18,R18,N18,N16,V15,M3,M5,L2,L4,V2,R2,N2,N4,V5,H17,H15, " &
			"J18,J16,B18,E18,G18,G16,B15,G4,B5,B2,E2,G2,J2,J4,H5,H3), " &
			"AINV:M10, " &--Address Inversion State for Address Bus
			"LDA_n:H8, " &--Load Input (Port A)
			"LDB_n:H12, " &--Load Input (Port B)
			"RWA_n:H10, " &--Read/Write Input (Port A)
			"RWB_n:L10, " &--Read/Write Input (Port B)
			"AP:P10, " &--Address Parity
			"PE_n:V10, " &--Address Parity Error
			"DKA:(F4,F16), " &--Data Input Clock
			"DKA_n:(F3,F17), " &--Data Input Clock
			"DKB:(P4,P16), " &--Data Input Clock
			"DKB_n:(P3,P17), " &--Data Input Clock
			"QKA:(C4,C16), " &--Data Output Clock
			"QKA_n:(D3,D17), " &--Data Output Clock
			"QKB:(U4,U16), " &--Data Output Clock
			"QKB_n:(T3,T17), " &--Data Output Clock
			"DQA:(C8,B7,C6,D5,D7,A4,F5,A6,A8, " &
			"C12,B13,C14,D15,D13,A16,F15,A14,A12), " &--Data Input/Output (Port A)
			"DQB:(U8,V7,U6,T5,T7,W4,P5,W6,W8, " &
			"U12,V13,U14,T15,T13,W16,P15,W14,W12), " &--Data Input/Output (Port B)
			"DNU:T10, " &--Do Not Use
			"DINVA:(D8,D12), " &--Data Inversion State (Port A)
			"DINVB:(T8,T12), " &--Data Inversion State (Port B)
			"QVLDA:(C3,C17), " &--Data Valid (Port A)
			"QVLDB:(U3,U17), " &--Data Valid (Port B)
			"CFG_n:D10, " &--Configuration bit
			"RST_n:K18, " &--Active Low Asynchronous RST
			"LBK_n:(A10,B10), " &--Loopback mode for control
			"TMS:K17, " &--JTAG Test Mode Select
			"TDI:K1, " &--JTAG Test Data In
			"TCK:K3, " &--JTAG Test Clock
			"TDO:K19, " &--JTAG Test Data Out
			"TRST_n:K2, " &--Reset pin for JTAG
			"VREF:(K8,K12,E4,E16,R4,R16), " &--Input Voltage Reference
			"VDD:(K7,K13,B1,D1,H1,M1,T1,V1,K5,G6,J6,L6,N6,E8,L8,R8,B9,D9,F9,P9,T9,V9,E10,R10, " &
			"B11,D11,F11,P11,T11,V11,E12,L12,R12,G14,J14,L14,N14,K15,B19,D19,H19,M19,T19,V19), " &
			"VDDQ:(F1,P1,A2,C2,U2,W2,B3,E3,J3,L3,R3,V3,D4,T4,A5,G5,N5,W5,B6,E6,R6,V6,C7,F7,P7,U7,B8,V8, " &
			"H9,K9,M9,C10,U10,H11,K11,M11,B12,V12,C13,F13,P13,U13,B14,E14,R14,V14,A15,G15,N15,W15,D16,T16, " &
			"B17,E17,J17,L17,R17,V17,A18,C18,U18,W18,F19,P19), " &
			"VSS:(A1,C1,E1,G1,J1,L1,N1,R1,U1,W1,A19,C19,E19,G19,J19,L19,N19,R19,U19,W19,D2,F2,H2,M2,P2,T2,D18,F18,H18,M18,P18,T18,  " &
			"A3,G3,N3,W3,A17,G17,N17,W17,B4,H4,K4,M4,V4,B16,H16,K6,K14,K16,M16,V16,C5,E5,J5,L5,R5,U5,C15,E15,J15,L15,R15,U15,D6,F6,H6,M6,P6,T6,D14,F14,H14,M14,P14,T14,  " &
			"A7,E7,H7,M7,R7,W7,A13,E13,H13,M13,R13,W13,G8,J8,N8,G12,J12,N12,A9,C9,E9,R9,U9,W9,A11,C11,E11,R11,U11,W11) "; 
			
	attribute TAP_SCAN_IN    of TDI    : signal is true;
	attribute TAP_SCAN_RESET of TRST_n : signal is true;
	attribute TAP_SCAN_OUT   of TDO    : signal is true;
	attribute TAP_SCAN_MODE  of TMS    : signal is true;
	attribute TAP_SCAN_CLOCK of TCK    : signal is (10.0e6, BOTH);

	attribute INSTRUCTION_LENGTH of CY7C4122KV13 : entity is 3;

	attribute INSTRUCTION_OPCODE of CY7C4122KV13 : entity is
		"EXTEST		(000)," &
	 	"IDCODE		(001)," &
	 	"SAMPLEZ	(010)," &-- Sample-Z
		"RESERV1	(011)," &
	 	"SAMPLE		(100)," &-- Sample
	 	"PRELOAD	(100)," &-- Preload
	 	"RESERV2	(101)," &
		"RESERV3	(110)," &
	 	"BYPASS		(111) ";

	attribute INSTRUCTION_CAPTURE of CY7C4122KV13: entity is "001";

	attribute INSTRUCTION_PRIVATE of CY7C4122KV13 : entity is
		"RESERV1, RESERV2, RESERV3"; 

	attribute IDCODE_REGISTER of CY7C4122KV13 : entity is
		"000"& -- Reserved for version number
		"11011010101010011"& -- Defines the type of SRAM
		"00000110100"& -- Unique ID for SRAM vendor
		"1";-- ID register Presence indicator

	attribute REGISTER_ACCESS of CY7C4122KV13 : entity is
		"BOUNDARY	(EXTEST,SAMPLEZ,SAMPLE)," &
		"BYPASS	(BYPASS)";

	attribute BOUNDARY_LENGTH of CY7C4122KV13 : entity is 136;

	attribute BOUNDARY_REGISTER of CY7C4122KV13 : entity is
		"0		(BC_7, DQA(17),		bidir,	X, 50, 0, Z)," &
		"1		(BC_7, DQA(10),		bidir,	X, 50, 0, Z)," &
		"2		(BC_7, DQA(16),		bidir,	X, 50, 0, Z)," &
		"3		(BC_4, *,	    	internal,	X)," &
		"4		(BC_7, DQA(14),		bidir,	X, 50, 0, Z)," &
		"5		(BC_4, *,	    	internal,	X)," &
		"6		(BC_9, QVLDA(1),	output2,	X)," &
		"7		(BC_9, QKA(1), 		output2,	X)," &
		"8		(BC_7, DQA(11),		bidir,	X, 50, 0, Z)," &
		"9		(BC_7, DQA(9),		bidir,	X, 50, 0, Z), " &
		"10		(BC_7, DINVA(1), 	bidir,	X, 50, 0, Z)," &
		"11		(BC_7, DQA(13),		bidir,	X, 50, 0, Z)," &
		"12		(BC_7, DQA(12),		bidir,	X, 50, 0, Z), " &
		"13		(BC_9, QKA_n(1), 	output2,	X), " &
		"14		(BC_4, *,	      	internal,	X)," &
		"15		(BC_7, DQA(15),		bidir,	X, 50, 0, Z)," &
		"16		(BC_4, DKA(1),		input,	X), " &
		"17		(BC_4, DKA_n(1),	input,	X), " &
		"18		(BC_4, *,	      	internal,	X)," &
		"19		(BC_4, *,	      	internal,	X)," &
		"20		(BC_4, *,	      	internal,	X), " &
		"21		(BC_4, *,	      	internal,	X), " &
		"22		(BC_4, *,	      	internal,	X)," &
		"23		(BC_4, *,	      	internal,	X)," &
		"24		(BC_4, RST_n,		input,	X), " &
		"25		(BC_4, *,	      	internal,	X), " &
		"26		(BC_4, *,	      	internal,	X)," &	
		"27		(BC_4, *,	      	internal,	X)," &
		"28		(BC_4, *,	      	internal,	X)," &
		"29		(BC_4, *,	      	internal,	X), " &
		"30		(BC_4, *,	      	internal,	X), " &
		"31		(BC_7, DQB(15),		bidir,	X, 49, 0, Z)," &
		"32		(BC_4, DKB(1),		input,	X)," &
		"33		(BC_4, DKB_n(1),	input,	X), " &
		"34		(BC_4, *,	     	internal,	X), " &
		"35		(BC_9, QKB_n(1), 	output2,	X)," &
		"36		(BC_7, DQB(12),		bidir,	X, 49, 0, Z)," &
		"37		(BC_7, DQB(13),		bidir,	X, 49, 0, Z), " &
		"38		(BC_7, DINVB(1), 	bidir,	X, 49, 0, Z), " &
		"39		(BC_7, DQB(9),		bidir,	X, 49, 0, Z)," &
		"40		(BC_7, DQB(11),		bidir,	X, 49, 0, Z)," &
		"41		(BC_9, QKB(1), 		output2,	X), " &
		"42		(BC_9, QVLDB(1), 	output2,	X), " &
		"43		(BC_4, *,	      	internal,	X)," &
		"44		(BC_4, *,	      	internal,	X)," &
		"45		(BC_7, DQB(10),		bidir,	X, 49, 0, Z), " &
		"46		(BC_7, DQB(17),		bidir,	X, 49, 0, Z)," &
		"47		(BC_7, DQB(16),		bidir,	X, 49, 0, Z)," &
		"48		(BC_7, DQB(14),		bidir,	X, 49, 0, Z)," &
		"49		(BC_2, *,			controlr,	0)," &
		"50		(BC_2, *,			controlr,	0)," &
		"51		(BC_9, PE_n, 		output2,	X)," &
		"52		(BC_4, A(15),		input,	X)," &
		"53		(BC_4, A(9),		input,	X)," &
		"54		(BC_4, *,	      	internal,	X)," &
		"55		(BC_4, AP,			input,	X)," &
		"56		(BC_4, A(2),		input,	X)," &
		"57		(BC_4, *,	      	internal,	X)," &
		"58		(BC_4, A(16),		input,	X)," &
		"59		(BC_4, A(10),		input,	X)," &
		"60		(BC_4, A(8),		input,	X)," &
		"61		(BC_4, A(12),		input,	X)," &
		"62		(BC_4, A(18),		input,	X)," &
		"63		(BC_4, RWB_n,		input,	X)," &
		"64		(BC_4, AINV,		input,	X), " &
		"65		(BC_4, A(17),		input,	X)," &
		"66		(BC_4, A(11),		input,	X)," &
		"67		(BC_4, A(7),		input,	X), " &
		"68		(BC_4, A(5),		input,	X), " &
		"69		(BC_4, A(19),		input,	X)," &
		"70		(BC_4, CK_n,		input,	X)," &
		"71		(BC_4, CK,  		input,	X), " &
		"72		(BC_4, A(20),		input,	X), " &
		"73		(BC_4, A(6),		input,	X)," &
		"74		(BC_4, LDB_n,		input,	X)," &
		"75		(BC_4, RWA_n,		input,	X), " &
		"76		(BC_4, LDA_n,		input,	X), " &
		"77		(BC_4, A(3),		input,	X)," &
		"78		(BC_4, A(21),		input,	X)," &
		"79		(BC_4, A(1),		input,	X), " &
		"80		(BC_4, *,	      	internal,	X), " &
		"81		(BC_4, A(4),		input,	X)," &
		"82		(BC_4, A(14),		input,	X)," &
		"83		(BC_4, A(0),		input,	X)," &
		"84		(BC_4, A(13),		input,	X), " &
		"85		(BC_4, CFG_n,		input,	X), " &
		"86		(BC_4, LBK_n(1),	input,	X)," &
		"87		(BC_4, LBK_n(0),	input,	X)," &
		"88		(BC_7, DQA(8),		bidir,	X, 50, 0, Z), " &
		"89		(BC_7, DQA(1),		bidir,	X, 50, 0, Z), " &
		"90		(BC_7, DQA(7),		bidir,	X, 50, 0, Z)," &
		"91		(BC_4, *,	      	internal,	X)," &
		"92		(BC_7, DQA(5),		bidir,	X, 50, 0, Z), " &
		"93		(BC_4, *,	      	internal,	X), " &
		"94		(BC_9, QVLDA(0), 	output2,	X)," &
		"95		(BC_9, QKA(0), 		output2,	X)," &
		"96		(BC_7, DQA(2),		bidir,	X, 50, 0, Z), " &
		"97		(BC_7, DQA(0),		bidir,	X, 50, 0, Z), " &
		"98		(BC_7, DINVA(0), 	bidir,	X, 50, 0, Z)," &
		"99 	(BC_7, DQA(4),		bidir,	X, 50, 0, Z)," &
		"100	(BC_7, DQA(3),		bidir,	X, 50, 0, Z), " &
		"101	(BC_9, QKA_n(0), 	output2,	X)," &
		"102	(BC_4, *,	      	internal,	X)," &
		"103	(BC_4, DKA_n(0),	input,	X)," &
		"104	(BC_4, DKA(0),		input,	X)," &
		"105	(BC_7, DQA(6),		bidir,	X, 50, 0, Z)," &
		"106	(BC_4, *,	      	internal,	X),"&
		"107	(BC_4, *,	      	internal,	X)," &
		"108	(BC_4, *,	      	internal,	X),"&
		"109	(BC_4, *,	      	internal,	X)," &
		"110	(BC_4, *,	      	internal,	X),"&
		"111	(BC_4, *,	      	internal,	X)," &
		"112	(BC_4, *,	      	internal,	X),"&
		"113	(BC_4, *,	      	internal,	X),"&
		"114	(BC_4, *,	      	internal,	X),"&
		"115	(BC_4, *,	      	internal,	X),"&
		"116	(BC_4, *,	      	internal,	X),"&
		"117	(BC_4, *,	      	internal,	X),"&
		"118	(BC_7, DQB(6),		bidir,	X, 49, 0, Z),"&
		"119	(BC_4, DKB(0),		input,	X)," &
		"120	(BC_4, DKB_n(0),	input,	X)," &
		"121	(BC_4, *,	      	internal,	X),"&
		"122	(BC_9, QKB_n(0), 	output2,	X)," &
		"123	(BC_7, DQB(3),		bidir,	X, 49, 0, Z),"&
		"124	(BC_7, DQB(4),		bidir,	X, 49, 0, Z),"&
		"125    (BC_7, DINVB(0), 	bidir,	X, 49, 0, Z)," &
		"126	(BC_7, DQB(0),		bidir,	X, 49, 0, Z),"&
		"127	(BC_7, DQB(2),		bidir,	X, 49, 0, Z),"&
		"128	(BC_9, QKB(0), 		output2,	X)," &
		"129    (BC_9, QVLDB(0), 	output2,	X)," &
		"130	(BC_4, *,	      	internal,	X),"&
		"131	(BC_4, *,	      	internal,	X),"&
		"132	(BC_7, DQB(1),		bidir,	X, 49, 0, Z),"&
		"133	(BC_7, DQB(8),		bidir,	X, 49, 0, Z),"&
		"134	(BC_7, DQB(7),		bidir,	X, 49, 0, Z),"&
		"135	(BC_7, DQB(5),		bidir,	X, 49, 0, Z)";
		
    end CY7C4122KV13;