BSDL Files Library for JTAG
The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BS/JTAG tools

ChipVORX ISP IP for Ultra Fast Flash Programming
BSDL File: PCI9030_PQF_r4 Download View details  


-- =======================================================================
--	Boundary Scan Description Language (BSDL) File
--
--	Product: PCI9030 (PLX Technology, Inc.)
--	Package: PQFP-176
--
-- =======================================================================
--    ****************************************************************
--    This BSDL has been validated for syntax and semantics compliance
--	to IEEE 1149.1.  It also passed all hardware validation tests, 
--	using the ASSET InterTech, Inc./Ensure DFT Services' 
--	BSDL Validation process.  
--
--	Ensure DFT Services
--	A Division of ASSET InterTech, Inc.
--	Ph: 603-886-6060
--    ****************************************************************
-- =======================================================================
--
-- IMPORTANT NOTE:
-- There are two compliance enables for this device.  The test engineer
-- must ensure these signals are set according to the compliance patterns,
-- prior to accessing this device for Boundary Scan testing.
-- Signals are BD_SEL_N_TEST, RST_N = 01 
-- =========================================================
--	Revision Control:
--
--	Version	Date		Reason for Change
-- 	*******	********	*****************
--	1.0	08/09/00	Initial Version
--				Randy West, ASSET InterTech, Inc.
--    2.0   09/26/00    Pin 53 (LEDon_N) was found to always stay
--                      high.  Re-generated this version with this
--                      pin as an internal cell.
--                      JKadaras, Ensure DFT Services
--    3.0   01/30/01    Device specification problems with pins 52 and 53
--                      being swapped in the original spec.  This is probably
--                      what caused pin 53 to fail.  Changed LEDon_N back to
--                      an output and swapped pin numbers to reflect
--                      the new device specification documents.  This update
--                      has not been hardware validated, but should work.
--                      LEDon_N is now pin 52.
--                      JKadaras, Ensure DFT Services
--    4.0	01/03/02	Changed Sample instruction to 0100 from xx01.   
--				Passes all hardware validation tests & sample tests.
--                      JKadaras, Ensure DFT Services
--
-- ======================================================================

entity PCI9030_PQF_r4 is

generic ( PHYSICAL_PIN_MAP : string := "PQFP_176" ) ;

port (
 -- Signal Name | Type and Dimension | Description
 -- Power and Ground Pins
VDD : linkage bit_vector ( 1 to 11 );  -- Power (+3.3V)
VI_O : linkage bit;  -- Voltage Input/Output
VSS : linkage bit_vector ( 1 to 14 );  -- Ground
 --Serial EEPROM Interface Pins
EECS : buffer bit;  -- Serial EEPROM Chip Select
EEDI : buffer bit;  -- Serial EEPROM Data In
EEDO : in bit;  -- Serial EEPROM Data Out
EESK : buffer bit;  -- Serial Data Clock
 -- Test and Debug Pins
TCK : in bit;  -- Test Clock
TDI : in bit;  -- Test Data In
TDO : out bit;  -- Test Data Out
BD_SEL_N_TEST : in bit;  -- Board Select/Test
TMS : in bit;  -- Test Mode Select
TRST_N : in bit;  -- Test Reset
 -- PCI System Bus Interface Pins
AD : inout bit_vector ( 31 downto 0 );  -- Address and Data
C_BE_N : in bit_vector ( 3 downto 0 );  -- Bus Command and Byte Enables
DEVSEL_N : out bit;  -- Device Select
ENUM_N : out bit;  -- Enumeration
FRAME_N : in bit;  -- Cycle Frame
IDSEL : in bit;  -- Initialization Device Select
INTA_N : out bit;  -- Interrupt A
IRDY_N : in bit;  -- Initiator Ready
LOCK_N : in bit;  -- Lock
PAR : inout bit;  -- Parity
PCLK : in bit;  -- Clock
PERR_N : out bit;  -- Parity Error
PME_N : out bit;  -- Power Management Event
RST_N : in bit;  -- Reset
SERR_N : out bit;  -- System Error
STOP_N : out bit;  -- Stop
TRDY_N : out bit;  -- Target Ready
 -- Local Bus Mode-Independent Interface Pins
BCLKo : buffer bit;  -- BCLK Out
CPCISW : in bit;  -- CompactPCI Switch
CS0_N : out bit;  -- Chip Select 0
CS1_N : out bit;  -- Chip Select 1
GPIO0_WAITo_N : inout bit;  -- General Purpose I/O 0 or WAIT Out
GPIO1_LLOCKo_N : inout bit;  -- General Purpose I/O 1 or LLOCK Out
GPIO2_CS2_N : inout bit;  -- General Purpose I/O 2 or Chip Select 2 Out
GPIO3_CS3_N : inout bit;  -- General Purpose I/O 3 or Chip Select 3 Out
GPIO8 : inout bit;  -- General Purpose I/O 8
LCLK : in bit;  -- Local Bus Clock
-- LEDon_N to linkage bit 9/26/00, r2, JK
-- LEDon_N to out bit 1/30/01, r3, JK
LEDon_N : out bit;  -- LED On
LGNT : buffer bit;  -- Local Bus Grant
LINTi1 : in bit;  -- Local Interrupt Input 1
LINTi2 : in bit;  -- Local Interrupt Input 2
LPMESET : in bit;  -- Local Power Management Event Set
LPMINT_N : buffer bit;  -- Local Power Management Interrupt
LREQ : in bit;  -- Local Bus Request
LRESETo_N : buffer bit;  -- Local Bus Reset Out
MODE : in bit;  -- Bus Mode
 -- Local Bus Mode-Dependent (Multiplexed/ Non-multiplexed) Interface Pins
ADS_N : out bit;  -- Address Strobe
ALE : out bit;  -- Address Enable Latch
BLAST_N : out bit;  -- Burst Last
BTERM_N : in bit;  -- Burst Terminate
GPIO4_LA27 : inout bit;  -- General Purpose I/O 4 or Address Bus
GPIO5_LA26 : inout bit;  -- General Purpose I/O 5 or Address Bus
GPIO6_LA25 : inout bit;  -- General Purpose I/O 6 or Address Bus
GPIO7_LA24 : inout bit;  -- General Purpose I/O 7 or Address Bus
LA : out bit_vector ( 23 downto 2 );  -- Address Bus
LAD : inout bit_vector ( 31 downto 0 );  -- Address/Data Bus
LBE_N : out bit_vector ( 3 downto 0 );  -- Byte Enables
LW_R_N : out bit;  -- Write/Read
RD_N : out bit;  -- Read Strobe
READY_N : in bit;  -- Local Ready Input
WR_N : out bit  -- Write Strobe
) ;

use STD_1149_1_1994.all ;

attribute COMPONENT_CONFORMANCE OF PCI9030_PQF_r4 : entity is
	"STD_1149_1_1993" ;

attribute PIN_MAP of PCI9030_PQF_r4 : entity is PHYSICAL_PIN_MAP ;

constant PQFP_176 : PIN_MAP_STRING :=
 -- Signal Name | Pin Numbers
 -- Power and Ground Pins
" VDD : ( 1, 14, 32, 45, 56, 70, 85, 100, 117, 133, 162 )," &
" VI_O : 53 ," &
" VSS : ( 13, 31, 44, 57, 66, 78, 88, 101, 113, 122, 132 ," &
  " 146, 163, 176 )," &
 --Serial EEPROM Interface Pins
" EECS : 158 ," &
" EEDI : 161 ," &
" EEDO : 159 ," &
" EESK : 160 ," &
 -- Test and Debug Pins
" TCK : 165 ," &
" TDI : 168 ," &
" TDO : 167 ," &
" BD_SEL_N_TEST : 112 ," &
" TMS : 166 ," &
" TRST_N : 164 ," &
 -- PCI System Bus Interface Pins
" AD : ( 173, 174, 175 , 2, 3, 4, 5, 6, 9, 10, 11, 12 ," &
  " 15, 16, 17, 18, 30, 33, 34, 35, 36, 37, 38, 39 ," &
  " 41, 42, 43, 46, 47, 48, 49, 50 )," &
" C_BE_N : ( 7, 19, 29, 40 )," &
" DEVSEL_N : 23 ," &
" ENUM_N : 51 ," &
" FRAME_N : 20 ," &
" IDSEL : 8 ," &
" INTA_N : 170 ," &
" IRDY_N : 21 ," &
" LOCK_N : 25 ," &
" PAR : 28 ," &
" PCLK : 172 ," &
" PERR_N : 26 ," &
" PME_N : 169 ," &
" RST_N : 171 ," &
" SERR_N : 27 ," &
" STOP_N : 24 ," &
" TRDY_N : 22 ," &
 -- Local Bus Mode-Independent Interface Pins
" BCLKo : 71 ," &
" CPCISW : 54 ," &
" CS0_N : 147 ," &
" CS1_N : 148 ," &
" GPIO0_WAITo_N : 154 ," &
" GPIO1_LLOCKo_N : 155 ," &
" GPIO2_CS2_N : 156 ," &
" GPIO3_CS3_N : 157 ," &
" GPIO8 : 94 ," &
" LCLK : 145 ," &
" LEDon_N : 52 ," &
" LGNT : 150 ," &
" LINTi1 : 152 ," &
" LINTi2 : 153 ," &
" LPMESET : 103 ," &
" LPMINT_N : 126 ," &
" LREQ : 151 ," &
" LRESETo_N : 149 ," &
" MODE : 76 ," &
 -- Local Bus Mode-Dependent (Multiplexed/ Non-multiplexed) Interface Pins
" ADS_N : 138 ," &
" ALE : 75 ," &
" BLAST_N : 139 ," &
" BTERM_N : 144 ," &
" GPIO4_LA27 : 137 ," &
" GPIO5_LA26 : 136 ," &
" GPIO6_LA25 : 135 ," &
" GPIO7_LA24 : 134 ," &
" LA : ( 131, 130, 129, 128, 127, 125, 124, 123 ," &
  " 121, 120, 119, 118, 116, 115, 114 ," &
  " 111, 110, 109, 108, 107, 106, 105 )," &
" LAD : ( 61, 62, 63, 64, 65, 67, 68, 69, 72, 73, 74, 77, 79 ," &
  " 80, 81, 82, 83, 84, 86, 87, 89, 90, 91, 92, 93, 95 ," &
  " 96, 97, 98, 99, 102, 104 )," &
" LBE_N : ( 55, 58, 59, 60 )," &
" LW_R_N : 142 ," &
" RD_N : 141 ," &
" READY_N : 143 ," &
" WR_N : 140 " ;

attribute TAP_SCAN_IN of TDI : signal is true ;
attribute TAP_SCAN_OUT of TDO : signal is true ;
attribute TAP_SCAN_MODE of TMS : signal is true ;
attribute TAP_SCAN_RESET of TRST_N : signal is true ;
attribute TAP_SCAN_CLOCK of TCK : signal is ( 1.0e6, BOTH ) ;

attribute COMPLIANCE_PATTERNS OF PCI9030_PQF_r4 : entity is
	"(BD_SEL_N_TEST, RST_N) (01)" ;

attribute INSTRUCTION_LENGTH of PCI9030_PQF_r4 : entity is 4 ;
attribute INSTRUCTION_OPCODE of PCI9030_PQF_r4 : entity is
	"BYPASS (1111)," &
	"EXTEST (0000)," &
	"SAMPLE (0100)," &
	"JTAG_PRIVATE (001X)," &
	"JTAG_PRIVATE (0001)," &
	"JTAG_PRIVATE (10XX)," &
	"JTAG_PRIVATE (110X)," &
	"JTAG_PRIVATE (1110)" ;

attribute INSTRUCTION_CAPTURE of PCI9030_PQF_r4 : entity is "xx01" ;

attribute INSTRUCTION_PRIVATE of PCI9030_PQF_r4 : entity is
	"JTAG_PRIVATE" ;

attribute REGISTER_ACCESS of PCI9030_PQF_r4 : entity is
	"BOUNDARY ( EXTEST, SAMPLE )," &
 	"BYPASS ( BYPASS )" ;

attribute BOUNDARY_LENGTH of PCI9030_PQF_r4 : entity is 236 ;
attribute BOUNDARY_REGISTER of PCI9030_PQF_r4 : entity is

--  num  | cell |     port      |   function | safe [ccell | disval | rslt]
--  ________________________________________________________________________

"235 ( BC_1, PME_N, OUTPUT2, 1, 235, 1, WEAK1 )," &
"234 ( BC_1, INTA_N, OUTPUT2, 1, 234, 1, WEAK1 )," &
"233 ( BC_4, *, INTERNAL, X )," &
"232 ( BC_4, PCLK, INPUT, X )," &
"231 ( BC_4, AD(31), INPUT, X )," &
"230 ( BC_1, AD(31), OUTPUT3, X, 182, 1, Z )," &
"229 ( BC_4, AD(30), INPUT, X )," &
"228 ( BC_1, AD(30), OUTPUT3, X, 182, 1, Z )," &
"227 ( BC_4, AD(29), INPUT, X )," &
"226 ( BC_1, AD(29), OUTPUT3, X, 182, 1, Z )," &
"225 ( BC_4, AD(28), INPUT, X )," &
"224 ( BC_1, AD(28), OUTPUT3, X, 182, 1, Z )," &
"223 ( BC_4, AD(27), INPUT, X )," &
"222 ( BC_1, AD(27), OUTPUT3, X, 182, 1, Z )," &
"221 ( BC_4, AD(26), INPUT, X )," &
"220 ( BC_1, AD(26), OUTPUT3, X, 182, 1, Z )," &
"219 ( BC_4, AD(25), INPUT, X )," &
"218 ( BC_1, AD(25), OUTPUT3, X, 182, 1, Z )," &
"217 ( BC_4, AD(24), INPUT, X )," &
"216 ( BC_1, AD(24), OUTPUT3, X, 182, 1, Z )," &
"215 ( BC_4, C_BE_N(3), INPUT, X )," &
"214 ( BC_4, IDSEL, INPUT, X )," &
"213 ( BC_4, AD(23), INPUT, X )," &
"212 ( BC_1, AD(23), OUTPUT3, X, 182, 1, Z )," &
"211 ( BC_4, AD(22), INPUT, X )," &
"210 ( BC_1, AD(22), OUTPUT3, X, 182, 1, Z )," &
"209 ( BC_4, AD(21), INPUT, X )," &
"208 ( BC_1, AD(21), OUTPUT3, X, 182, 1, Z )," &
"207 ( BC_4, AD(20), INPUT, X )," &
"206 ( BC_1, AD(20), OUTPUT3, X, 182, 1, Z )," &
"205 ( BC_4, AD(19), INPUT, X )," &
"204 ( BC_1, AD(19), OUTPUT3, X, 182, 1, Z )," &
"203 ( BC_4, AD(18), INPUT, X )," &
"202 ( BC_1, AD(18), OUTPUT3, X, 182, 1, Z )," &
"201 ( BC_4, AD(17), INPUT, X )," &
"200 ( BC_1, AD(17), OUTPUT3, X, 182, 1, Z )," &
"199 ( BC_4, AD(16), INPUT, X )," &
"198 ( BC_1, AD(16), OUTPUT3, X, 182, 1, Z )," &
"197 ( BC_4, C_BE_N(2), INPUT, X )," &
"196 ( BC_1, *, CONTROL, 1 )," &
"195 ( BC_4, FRAME_N, INPUT, X )," &
"194 ( BC_4, IRDY_N, INPUT, X )," &
"193 ( BC_1, TRDY_N, OUTPUT3, X, 196, 1, Z )," &
"192 ( BC_1, DEVSEL_N, OUTPUT3, X, 196, 1, Z )," &
"191 ( BC_1, STOP_N, OUTPUT3, X, 196, 1, Z )," &
"190 ( BC_4, LOCK_N, INPUT, X )," &
"189 ( BC_1, PERR_N, OUTPUT3, X, 188, 1, Z )," &
"188 ( BC_1, *, CONTROL, 1 )," &
"187 ( BC_1, SERR_N, OUTPUT2, 1, 187, 1, WEAK1 )," &
"186 ( BC_4, PAR, INPUT, X )," &
"185 ( BC_1, PAR, OUTPUT3, X, 184, 1, Z )," &
"184 ( BC_1, *, CONTROL, 1 )," &
"183 ( BC_4, C_BE_N(1), INPUT, X )," &
"182 ( BC_1, *, CONTROL, 1 )," &
"181 ( BC_4, AD(15), INPUT, X )," &
"180 ( BC_1, AD(15), OUTPUT3, X, 182, 1, Z )," &
"179 ( BC_4, AD(14), INPUT, X )," &
"178 ( BC_1, AD(14), OUTPUT3, X, 182, 1, Z )," &
"177 ( BC_4, AD(13), INPUT, X )," &
"176 ( BC_1, AD(13), OUTPUT3, X, 182, 1, Z )," &
"175 ( BC_4, AD(12), INPUT, X )," &
"174 ( BC_1, AD(12), OUTPUT3, X, 182, 1, Z )," &
"173 ( BC_4, AD(11), INPUT, X )," &
"172 ( BC_1, AD(11), OUTPUT3, X, 182, 1, Z )," &
"171 ( BC_4, AD(10), INPUT, X )," &
"170 ( BC_1, AD(10), OUTPUT3, X, 182, 1, Z )," &
"169 ( BC_4, AD(9), INPUT, X )," &
"168 ( BC_1, AD(9), OUTPUT3, X, 182, 1, Z )," &
"167 ( BC_4, AD(8), INPUT, X )," &
"166 ( BC_1, AD(8), OUTPUT3, X, 182, 1, Z )," &
"165 ( BC_4, C_BE_N(0), INPUT, X )," &
"164 ( BC_4, AD(7), INPUT, X )," &
"163 ( BC_1, AD(7), OUTPUT3, X, 182, 1, Z )," &
"162 ( BC_4, AD(6), INPUT, X )," &
"161 ( BC_1, AD(6), OUTPUT3, X, 182, 1, Z )," &
"160 ( BC_4, AD(5), INPUT, X )," &
"159 ( BC_1, AD(5), OUTPUT3, X, 182, 1, Z )," &
"158 ( BC_4, AD(4), INPUT, X )," &
"157 ( BC_1, AD(4), OUTPUT3, X, 182, 1, Z )," &
"156 ( BC_4, AD(3), INPUT, X )," &
"155 ( BC_1, AD(3), OUTPUT3, X, 182, 1, Z )," &
"154 ( BC_4, AD(2), INPUT, X )," &
"153 ( BC_1, AD(2), OUTPUT3, X, 182, 1, Z )," &
"152 ( BC_4, AD(1), INPUT, X )," &
"151 ( BC_1, AD(1), OUTPUT3, X, 182, 1, Z )," &
"150 ( BC_4, AD(0), INPUT, X )," &
"149 ( BC_1, AD(0), OUTPUT3, X, 182, 1, Z )," &
"148 ( BC_1, ENUM_N, OUTPUT2, 1, 148, 1, WEAK1 )," &
-- "147 ( BC_1, *, INTERNAL, 1 )," &
-- LEDon_N to linkage bit 9/26/00, r2, JK
-- LEDon_N to OC out bit 1/30/01, r3, JK
"147 ( BC_1, LEDon_N, OUTPUT2, 1, 147, 1, WEAK1 )," &
"146 ( BC_4, CPCISW, INPUT, X )," &
"145 ( BC_1, LBE_N(3), OUTPUT3, X, 32, 1, Z )," &
"144 ( BC_1, LBE_N(2), OUTPUT3, X, 32, 1, Z )," &
"143 ( BC_1, LBE_N(1), OUTPUT3, X, 32, 1, Z )," &
"142 ( BC_1, LBE_N(0), OUTPUT3, X, 32, 1, Z )," &
"141 ( BC_4, LAD(31), INPUT, X )," &
"140 ( BC_1, LAD(31), OUTPUT3, X, 106, 1, Z )," &
"139 ( BC_4, LAD(30), INPUT, X )," &
"138 ( BC_1, LAD(30), OUTPUT3, X, 106, 1, Z )," &
"137 ( BC_4, LAD(29), INPUT, X )," &
"136 ( BC_1, LAD(29), OUTPUT3, X, 106, 1, Z )," &
"135 ( BC_4, LAD(28), INPUT, X )," &
"134 ( BC_1, LAD(28), OUTPUT3, X, 106, 1, Z )," &
"133 ( BC_4, LAD(27), INPUT, X )," &
"132 ( BC_1, LAD(27), OUTPUT3, X, 106, 1, Z )," &
"131 ( BC_4, LAD(26), INPUT, X )," &
"130 ( BC_1, LAD(26), OUTPUT3, X, 106, 1, Z )," &
"129 ( BC_4, LAD(25), INPUT, X )," &
"128 ( BC_1, LAD(25), OUTPUT3, X, 106, 1, Z )," &
"127 ( BC_4, LAD(24), INPUT, X )," &
"126 ( BC_1, LAD(24), OUTPUT3, X, 106, 1, Z )," &
"125 ( BC_1, BCLKo, OUTPUT2, X )," &
"124 ( BC_4, LAD(23), INPUT, X )," &
"123 ( BC_1, LAD(23), OUTPUT3, X, 106, 1, Z )," &
"122 ( BC_4, LAD(22), INPUT, X )," &
"121 ( BC_1, LAD(22), OUTPUT3, X, 106, 1, Z )," &
"120 ( BC_4, LAD(21), INPUT, X )," &
"119 ( BC_1, LAD(21), OUTPUT3, X, 106, 1, Z )," &
"118 ( BC_1, ALE, OUTPUT3, X, 32, 1, Z )," &
"117 ( BC_4, MODE, INPUT, X )," &
"116 ( BC_4, LAD(20), INPUT, X )," &
"115 ( BC_1, LAD(20), OUTPUT3, X, 106, 1, Z )," &
"114 ( BC_4, LAD(19), INPUT, X )," &
"113 ( BC_1, LAD(19), OUTPUT3, X, 106, 1, Z )," &
"112 ( BC_4, LAD(18), INPUT, X )," &
"111 ( BC_1, LAD(18), OUTPUT3, X, 106, 1, Z )," &
"110 ( BC_4, LAD(17), INPUT, X )," &
"109 ( BC_1, LAD(17), OUTPUT3, X, 106, 1, Z )," &
"108 ( BC_4, LAD(16), INPUT, X )," &
"107 ( BC_1, LAD(16), OUTPUT3, X, 106, 1, Z )," &
"106 ( BC_1, *, CONTROL, 1 )," &
"105 ( BC_4, LAD(15), INPUT, X )," &
"104 ( BC_1, LAD(15), OUTPUT3, X, 106, 1, Z )," &
"103 ( BC_4, LAD(14), INPUT, X )," &
"102 ( BC_1, LAD(14), OUTPUT3, X, 106, 1, Z )," &
"101 ( BC_4, LAD(13), INPUT, X )," &
"100 ( BC_1, LAD(13), OUTPUT3, X, 106, 1, Z )," &
"99 ( BC_4, LAD(12), INPUT, X )," &
"98 ( BC_1, LAD(12), OUTPUT3, X, 106, 1, Z )," &
"97 ( BC_4, LAD(11), INPUT, X )," &
"96 ( BC_1, LAD(11), OUTPUT3, X, 106, 1, Z )," &
"95 ( BC_4, LAD(10), INPUT, X )," &
"94 ( BC_1, LAD(10), OUTPUT3, X, 106, 1, Z )," &
"93 ( BC_4, LAD(9), INPUT, X )," &
"92 ( BC_1, LAD(9), OUTPUT3, X, 106, 1, Z )," &
"91 ( BC_4, LAD(8), INPUT, X )," &
"90 ( BC_1, LAD(8), OUTPUT3, X, 106, 1, Z )," &
"89 ( BC_4, LAD(7), INPUT, X )," &
"88 ( BC_1, LAD(7), OUTPUT3, X, 106, 1, Z )," &
"87 ( BC_4, GPIO8, INPUT, X )," &
"86 ( BC_1, GPIO8, OUTPUT3, X, 85, 1, Z )," &
"85 ( BC_1, *, CONTROL, 1 )," &
"84 ( BC_4, LAD(6), INPUT, X )," &
"83 ( BC_1, LAD(6), OUTPUT3, X, 106, 1, Z )," &
"82 ( BC_4, LAD(5), INPUT, X )," &
"81 ( BC_1, LAD(5), OUTPUT3, X, 106, 1, Z )," &
"80 ( BC_4, LAD(4), INPUT, X )," &
"79 ( BC_1, LAD(4), OUTPUT3, X, 106, 1, Z )," &
"78 ( BC_4, LAD(3), INPUT, X )," &
"77 ( BC_1, LAD(3), OUTPUT3, X, 106, 1, Z )," &
"76 ( BC_4, LAD(2), INPUT, X )," &
"75 ( BC_1, LAD(2), OUTPUT3, X, 106, 1, Z )," &
"74 ( BC_4, LAD(1), INPUT, X )," &
"73 ( BC_1, LAD(1), OUTPUT3, X, 106, 1, Z )," &
"72 ( BC_4, LPMESET, INPUT, X )," &
"71 ( BC_4, LAD(0), INPUT, X )," &
"70 ( BC_1, LAD(0), OUTPUT3, X, 106, 1, Z )," &
"69 ( BC_1, LA(2), OUTPUT3, X, 54, 1, Z )," &
"68 ( BC_1, LA(3), OUTPUT3, X, 54, 1, Z )," &
"67 ( BC_1, LA(4), OUTPUT3, X, 54, 1, Z )," &
"66 ( BC_1, LA(5), OUTPUT3, X, 54, 1, Z )," &
"65 ( BC_1, LA(6), OUTPUT3, X, 54, 1, Z )," &
"64 ( BC_1, LA(7), OUTPUT3, X, 54, 1, Z )," &
"63 ( BC_1, LA(8), OUTPUT3, X, 54, 1, Z )," &
"62 ( BC_4, *, INTERNAL, X )," &
"61 ( BC_1, LA(9), OUTPUT3, X, 54, 1, Z )," &
"60 ( BC_1, LA(10), OUTPUT3, X, 54, 1, Z )," &
"59 ( BC_1, LA(11), OUTPUT3, X, 54, 1, Z )," &
"58 ( BC_1, LA(12), OUTPUT3, X, 54, 1, Z )," &
"57 ( BC_1, LA(13), OUTPUT3, X, 54, 1, Z )," &
"56 ( BC_1, LA(14), OUTPUT3, X, 54, 1, Z )," &
"55 ( BC_1, LA(15), OUTPUT3, X, 54, 1, Z )," &
"54 ( BC_1, *, CONTROL, 1 )," &
"53 ( BC_1, LA(16), OUTPUT3, X, 54, 1, Z )," &
"52 ( BC_1, LA(17), OUTPUT3, X, 54, 1, Z )," &
"51 ( BC_1, LA(18), OUTPUT3, X, 54, 1, Z )," &
"50 ( BC_1, LPMINT_N, OUTPUT2, X )," &
"49 ( BC_1, LA(19), OUTPUT3, X, 54, 1, Z )," &
"48 ( BC_1, LA(20), OUTPUT3, X, 54, 1, Z )," &
"47 ( BC_1, LA(21), OUTPUT3, X, 54, 1, Z )," &
"46 ( BC_1, LA(22), OUTPUT3, X, 54, 1, Z )," &
"45 ( BC_1, LA(23), OUTPUT3, X, 54, 1, Z )," &
"44 ( BC_4, GPIO7_LA24, INPUT, X )," &
"43 ( BC_1, GPIO7_LA24, OUTPUT3, X, 42, 1, Z )," &
"42 ( BC_1, *, CONTROL, 1 )," &
"41 ( BC_4, GPIO6_LA25, INPUT, X )," &
"40 ( BC_1, GPIO6_LA25, OUTPUT3, X, 39, 1, Z )," &
"39 ( BC_1, *, CONTROL, 1 )," &
"38 ( BC_4, GPIO5_LA26, INPUT, X )," &
"37 ( BC_1, GPIO5_LA26, OUTPUT3, X, 36, 1, Z )," &
"36 ( BC_1, *, CONTROL, 1 )," &
"35 ( BC_4, GPIO4_LA27, INPUT, X )," &
"34 ( BC_1, GPIO4_LA27, OUTPUT3, X, 33, 1, Z )," &
"33 ( BC_1, *, CONTROL, 1 )," &
"32 ( BC_1, *, CONTROL, 1 )," &
"31 ( BC_1, ADS_N, OUTPUT3, X, 32, 1, Z )," &
"30 ( BC_1, BLAST_N, OUTPUT3, X, 32, 1, Z )," &
"29 ( BC_1, WR_N, OUTPUT3, X, 32, 1, Z )," &
"28 ( BC_1, *, CONTROL, 1 )," &
"27 ( BC_1, RD_N, OUTPUT3, X, 28, 1, Z )," &
"26 ( BC_1, LW_R_N, OUTPUT3, X, 32, 1, Z )," &
"25 ( BC_4, READY_N, INPUT, X )," &
"24 ( BC_4, BTERM_N, INPUT, X )," &
"23 ( BC_4, LCLK, INPUT, X )," &
"22 ( BC_1, CS0_N, OUTPUT3, X, 32, 1, Z )," &
"21 ( BC_1, CS1_N, OUTPUT3, X, 32, 1, Z )," &
"20 ( BC_1, LRESETo_N, OUTPUT2, X )," &
"19 ( BC_1, LGNT, OUTPUT2, X )," &
"18 ( BC_4, LREQ, INPUT, X )," &
"17 ( BC_4, LINTi1, INPUT, X )," &
"16 ( BC_4, LINTi2, INPUT, X )," &
"15 ( BC_4, GPIO0_WAITo_N, INPUT, X )," &
"14 ( BC_1, GPIO0_WAITo_N, OUTPUT3, X, 13, 1, Z )," &
"13 ( BC_1, *, CONTROL, 1 )," &
"12 ( BC_4, GPIO1_LLOCKo_N, INPUT, X )," &
"11 ( BC_1, GPIO1_LLOCKo_N, OUTPUT3, X, 10, 1, Z )," &
"10 ( BC_1, *, CONTROL, 1 )," &
"9 ( BC_4, GPIO2_CS2_N, INPUT, X )," &
"8 ( BC_1, GPIO2_CS2_N, OUTPUT3, X, 7, 1, Z )," &
"7 ( BC_1, *, CONTROL, 1 )," &
"6 ( BC_4, GPIO3_CS3_N, INPUT, X )," &
"5 ( BC_1, GPIO3_CS3_N, OUTPUT3, X, 4, 1, Z )," &
"4 ( BC_1, *, CONTROL, 1 )," &
"3 ( BC_1, EECS, OUTPUT2, X )," &
"2 ( BC_4, EEDO, INPUT, X )," &
"1 ( BC_1, EESK, OUTPUT2, X )," &
"0 ( BC_1, EEDI, OUTPUT2, X )" ;

end PCI9030_PQF_r4 ;

This library contains 11039 BSDL files (for 7844 distinct entities) from 72 vendors
Last BSDL model (idt82v3910) was added on Sep 29, 2018 16:58
info@bsdl.info